on FPGA simulation

Al Kossow wrote: Yes, that's quite important, and although the application note mentions it, it doesn't show it in most of the diagrams. The author really should have called more attention to it. My VHDL version has two outputs, which are the output of the XOR synchronized to each of the clock domains. I did something that many people consider to be a no-no. I did the dual-rank synchronization with the first FF clocked by the inverted clock, to reduce the latency. The reason people say that's a no-no is that it doesn't do as good a job at reducing the probability of metastability. However, the probability of metastability with a clock of frequency f with opposite-phase FFs is exactly the same as the probability with conventional same-phase FFs at a frequency of 2f (provided that the FF characteristics are otherwise identical), so if you do analysis for 2f and get acceptable results, you can use frequency f with opposite phases. Eric