27 Oct
2017
27 Oct
'17
1:58 p.m.
On 10/27/2017 01:01 PM, Paul Koning wrote:
Oh yes, and if you look at the wire lists (on
Bitsavers) you will get the length of every wire in the machine. The trouble is that,
even if you use the documented delay per foot, things don't necessarily match. The
stated logic stage delay is 5 ns, no special numbers given for twisted pair drivers. In
my model, I do everything in 5 ns multiples (to keep the simulation time under control).
That works pretty closely, but not 100 percent, not for some of the CPU pieces. The other
thing that's nuts is that the CPU effectively has a 20-phase clock: the documentation
shows clock signals with offsets from the reference time given in multiples of 5
nanoseconds (for the 100 ns clock period). And yes, it matters. And yes, many (I'm
not sure about all) of the 20 phases are actually used in the CPU.
I can't recall, but didn't the 6600 have something like 10 clock
sources, all kept synchronized?
In any case, it's a gross oversimplification to say that the 6600 had a
10 MHz clock.
--Chuck