2 Sep
2014
2 Sep
'14
3:12 p.m.
Howdy,
On Tue, Sep 2, 2014 at 2:08 PM, Tony Duell <ard at p850ug1.demon.co.uk> wrote:
Yes, drawn as an OR with inverter bubbles at the inputs.
Hmm.. negative logic vs. positive logic.. that's a new one to me. Sure, I
get what you're saying, but at my current level it really seems like an
unnecessary complication / confusion. The data sheet calls out the 7408 as
"quad AND gate", and that's how it behaves, so that's how I expect a
7408
to be drawn.. as AND gates.
As time goes on and experience grows, I'm sure the 'wisdom' of their
choices will become more evident. At the moment, it's a distraction.
So then, let's move on to the section on configuring the switches on the
board. Frankly, it appears not only confusing and just plain wrong, it also
appears to contradict itself. I think this is the stuff that Brent was
mentioning earlier - if you set those switches the way the doc indicates,
the memory gets mapped to the top-end of the 64K range, as opposed to the
bottom end. That one I verified. Also, the switches on the board are in
reverse order vs. the switch tables drawn in the manual.
Then there's the strange statement.. "closed=0 open=1", bottom of p.1-5.
Now that defies every convention known to man.. 0=false=open=off /
1=true=closed=on in my world.
(as ever, docs are at nerp.net/~legendre/altair/
Just noticed some errors in the CCS DRAM board schematic. Both U4
(74LS20)
and U5 (7400) are drawn as an OR gates. I'm
sure there's more..
I've not seen the schamtics, but are they drawn, perhaps, as OR gates
_with inverting circles on the inputs_? Rememebr that a positive logic
AND gate is a negative logic OR gate (De Morgan's lwa, essentially). That
is, if you have 2 active low signals (signals that are true when low/0),
and feed them into am AND gate like a 7408, then output, if considerd
also to be actiuve low, is true is either of the inputs is true
(translation : the output of an AND gate is 0 if either of the inputs is
0). So calling it an OR gate makes sense.
-tony