2 Nov
2013
2 Nov
'13
6:07 p.m.
On Nov 2, 2013, at 17:13, John Wilson <wilson at dbit.com> wrote:
You could probably pair it with a small CPLD or FPGA to help
with the shifting (if, as Chuck pointed out, the SPI hardware won't
do the trick). That could add as little as $5 to your BOM, even in
single-unit quantities.
- Dave
On Sat, Nov 02, 2013 at 08:17:47PM -0000, Robert
Jarratt wrote:
I had a look and it seems close to what I would need, but possibly not
quite. It says it will do 400mips, which for a sampling frequency of 40MhZ
would give me 10 instructions per sample (crude assumption I know), but it
is not clear to me if each core does 400mips, or if that is 400mips
aggregated across 8 cores (which seems more likely), which would give my
just 1 instructions per sample. Do you know which it is?
It's the second one, so I was picturing a little hardware help. If something
outside helps measure pulse lengths, shoveling those into the chip isn't so
bad, and then the receiver thread can hand off to a mark-detection thread or
whatever and keep the main code path short.
XMOS went insane about a year ago and replaced all the plain English on
their website with severe market-talk so you can't tell what anything really
is. The actual point is that on a 100 MHz clock, or maybe 125 MHz or
possibly 175 MHz with newer chips, the processor executes one instruction
from each of the next four threads in line, and then moves them to the back
of the line (which is still the front of the line if you're only using <= 4
threads).