In article <20101202090317.GA27897 at Update.UU.SE>,
Pontus Pihlgren <pontus at Update.UU.SE> writes:
On Thu, Dec 02, 2010 at 01:56:33AM -0700, Richard
wrote:
See, for example, this article written by the
author of Varnish.
<http://queue.acm.org/detail.cfm?id=1814327>
Well, It migth not come as a surprise that I've already read that :) But
my Computer Architecture professor pounded the message into me already
when I studied for my computer science degree.
I don't recall cache being discussed at all when I was an undergrad
(1982-1986), but it came up in computer architecture courses when I
was a grad student. Since then, cache (or memory latency in general)
has become the dominating factor in high performance systems.
The Cell processor takes what you might call an "architectural left
turn" as a result of the size of off-chip memory latencies, by putting
fast SRAM in the SPU processors and treating off-chip memory access as
essentially an I/O operation akin to getting data from a disk drive.
SPU processors have no cache and no direct external memory bus.
--
"The Direct3D Graphics Pipeline" -- DirectX 9 draft available for download
<http://legalizeadulthood.wordpress.com/the-direct3d-graphics-pipeline/>
Legalize Adulthood! <http://legalizeadulthood.wordpress.com>