13 Nov
2011
13 Nov
'11
1:50 p.m.
On Sun, Nov 13, 2011 at 15:29, Tony Duell <ard at p850ug1.demon.co.uk> wrote:
And this is what bothers me _a lot_. If the device is
not fully
documented (as in, if I cann not predict its behavious when I load a
paritcular configuration file)m, then I can't know excatly what it is
doing to my design. So when my deisgn doesn't work, I am left trusting
that the manufacutrers tools and devices both work properly . Which is
certainyl somethign that I am not prepared to do. I want to know just
what is going wrong and why (nost likely -- 99.999% of the time -- it's
my desing that's wrong, but I want to be able to be sure of that).
I'm a bit new to the FPGA field but AFAICT the tools (at least Xlinix)
do tell you _how_ your design is implemented on the FPGA: this pin is
connected to that logic block, which is located there (physically on
the chip), connected on these lines...
The logic elements are are documented, at least as well as a typical
74xx chip. So, once you have run the tools and have generated the
bitstream you should know very precisely how each signal is connected
to each other. You may not know how the bitstream encodes the
connections and the LUT tables, but if you trust that the tool tells
you accurately what is encoded, you should have a known wiring on the
FPGA.
But by his noodliness, the GUI Xilinx IDE is a hog. I'm running it on
an older Windows box in our Lab and it just crawls - but a) I _am_ in
the situation where I can only dump the configuration onto the chip
from a windows box (because I am cheap and only have
the parallel
cable) and b) when I last tried to run the Linux version of the IDE on
my main computer (quite powerful and gobs of RAM) it was an unholy
crappy mess. This may have been version 11, so maybe it's gotten
better - but for now I'll avoid polluting my filesystem with it.
Oh, and let's not even talk about the licensing legalese of the "free"
WebPack. Please. Keyboards might get broken and screens smashed.
Joe.
--
Joachim Thiemann :: http://www.tsp.ece.mcgill.ca/~jthiem1