16 Nov
2011
16 Nov
'11
10:48 a.m.
On Nov 16, 2011, at 1:15 PM, Chuck Guzis wrote:
On 15 Nov 2011 at 20:40, Keith Monahan wrote:
Well. Technically, you CAN run an FPGA or CPLD completely combinationally (a real CPLD,
after all, is basically a bunch of PALs glued together; Altera's MAX II
"CPLDs" are really just tiny FPGAs). There's no requirement to use any
registers at all. However, it drives the timing closure engines completely nuts because
they're designed to analyze synchronous designs. You can write the HDL any way you
want.
FWIW, I love simulation with FPGAs. It usually
reveals my beginner
mistakes, and is a pretty powerful tool to help test your design.
While I haven't done enough to demonstrate it, there are differences
between simulation and real hardware.
This and Tony's comment about using discrete logic rather than FPGA
points up an interesting, but important, limitation of FPGAs (and
CPLDs): they're clocked designs.
While Tony can use his 7400-series logic to implement an asynchronous
design, almost all FPGA implementations must have a clock of some
sort. Achronix is the only vendor that I can recall offhand
even discussing
aysnchronous FPGAs--and it's not even clear to me if they're still
offering them. Simulation must be a nightmare.
Their stuff looked nice, but like so many other recent challengers to FPGAs these days
(like those guys with the math-specific chip, etc), I haven't seen anything come out
that's really usable.
- Dave