26 Apr
2013
26 Apr
'13
4:54 p.m.
On Apr 26, 2013, at 7:42 PM, ben wrote:
On 4/25/2013 9:49 PM, David Riley wrote:
Well, that's one thing. Most of Altera's examples use their schematic
entry tool to instantiate a bunch of big black boxes that contain all
the bells and whistles (an SDRAM controller is a fairly complex thing,
ESPECIALLY DDR ones). I wish they wouldn't do that; it's laziness on
their part and HDL examples would be closer to what a lot of people
use in the real world.
For things like SDRAM controllers, DDR or not, you'll usually use one
of their IP cores. You should; they're free, and a controller like
that takes a LONG time to implement and debug (if you thought a DRAM
controller in 7400 parts was complex, just wait until you see the
timing calibration stuff that goes into DDR2 and DDR3).
When we see any of our customers doing FPGA
design by schematic entry,
it's usually a sign that something is dreadfully wrong with their
engineering department, because it's akin to trying to build a rocket
out of bubble gum and paperclips (at least with what modern FPGAs are
purposed for). Just don't do it. Learn Verilog or VHDL, or better
yet both. They will take you far.
Well I have been digging for information on using the DE0 board
on the net. It seems to be TWO types of information. A) Use schematic
entry for the push button switches. B) Use the latest bells and whistles
to have everything auto compiled for you. What I am looking for is 1) Generic SDRAM interface
with a 25 Mhz clock.
2) A Industry Standard Uart interface. 3) Generic flash controller interface. I don't
see that around. Also a good generic POWER up reset
circuit would be handy.
You might actually want to look into Qsys, which is Altera's GUI-
driven system generation interface. That actually lets you get up
and going rather quickly with all the interfaces you mentioned
above. When you write your own logic (e.g. a CPU core), it's not
*too* hard to bolt it on using Qsys, which does all the drudgery
of making the buses and address decoders for you.
Of course, it doesn't:
1) Give you a sense of how much work or logic goes into designing
bus multiplexers or address decoders
2) Show you how much complexity you add to address decoders by
making ALL YOUR REGISTERS FOR EVERYTHING go in one contiguous
address space with no gaps (yes, I had coworkers who did this in
HDL as well)
It's also not portable. But it's not a terrible start if you
want to just get up and running with an FPGA and a UART.
I'll be glad to send you a simple UART I made in Verilog that I
reuse in a lot of my projects. It's not fancy, and it doesn't
conform to any standard bus, but it's easy to glue to things. I
can also send you some simple projects for the DE1 board, which
should make for a nice exercise to port to the DE0 board (which
is quite similar in a lot of ways). I also have a peek/poke
unit entirely in Verilog using that same UART to do simple reads
and writes over Wishbone, which is the bus used by a lot of
OpenCores projects (and is nearly identical to Altera's Avalon
bus).
- Dave