on FPGA simulation

On 17 Nov 2011 at 0:03, Keith Monahan wrote: I think not quite what I had in mind. The self-timed design that essentially outputs a "done" signal when the product is finally formed. The verilog for this appears to reflect a fixed-time multiplier--at least there's no "done" output. Years ago, asynchronous computing was a hot topic--essentially, instructions were unclocked and took however long it required to signals to propogate through the logic to complete. That was the gist of Achronix' idea--that you could get some freakingly fast computation out of a clockless design. I also recall that the Philco System 2000 was one of the few commercial versions utilizing that idea. "Asynchronous" was part of their advertising campaign--and, for a very short time, they had one of the fastest transistorized machines. --Chuck P.S. I won't even broach the subject of reversible computation... :)