Jim Battle wrote:
This shows the use of two hidden registers, W and Z --
they are
analogous to another 16b BC pair. These hold the immediate 16b address
fetch, since the CPU needs to hold a 16b value for the duration of that
instruction that isn't retained afterward.
Yes, I think I've seen somewhere that W and Z were used to assemble a
temporary 16b address - however, that's a different kettle of fish; this chap
was wondering how multi-byte instructions (i.e. where the opcode itself is
longer than a single byte) get decoded.
It does seem logical (to both of us, anyway) that it's just a set of
flip-flops set by the prefix bytes to indicate different states - but so far
it seems that this isn't actually documented anywhere (presumably because it
doesn't *need* to be as far as anyone using the CPU is concerned)
I have the Zaks 'fat book' (and the Zilog A4-sized reference publication) but
unfortunately they're stuck in storage :-(
cheers
Jules