16 Nov
2011
16 Nov
'11
10:32 a.m.
On 11/16/2011 11:15 AM, Chuck Guzis wrote:
While Tony can use his 7400-series logic to implement an asynchronous
design, almost all FPGA implementations must have a clock of some
sort.
Not every design employing logic is a CPU and not all employ clocked
logic.
I thought that was just to cover up the fact the logic glitches.
Someone who wants to substitute, say, a CPLD for a
bunch of unclocked
TTL is going to have to come up with a clock--and then determine how
that will affect function.
Achronix is the only vendor that I can recall offhand even discussing
aysnchronous FPGAs--and it's not even clear to me if they're still
offering them. Simulation must be a nightmare.
Why? It just points out the new logic has lots routing timing skew.
--Chuck
Ben.