26 Apr
2013
26 Apr
'13
5:45 p.m.
On 4/26/2013 5:54 PM, David Riley wrote:
For things like SDRAM controllers, DDR or not, you'll usually use one
of their IP cores. You should; they're free, and a controller like
that takes a LONG time to implement and debug (if you thought a DRAM
controller in 7400 parts was complex, just wait until you see the
timing calibration stuff that goes into DDR2 and DDR3).
What ip core to use, is my problem.
I guess I could order the DE1 board to replace the DE0.
What was used in the PDP 11 setup I wonder.
You might actually want to look into Qsys, which is
Altera's GUI-
driven system generation interface. That actually lets you get up
and going rather quickly with all the interfaces you mentioned
above. When you write your own logic (e.g. a CPU core), it's not
*too* hard to bolt it on using Qsys, which does all the drudgery
of making the buses and address decoders for you.
I am not sure what I can use nowdays, everthing is $$$ for the IP
stuff.
It's also not portable. But it's not a
terrible start if you
want to just get up and running with an FPGA and a UART.
I'll be glad to send you a simple UART I made in Verilog that I
reuse in a lot of my projects. It's not fancy, and it doesn't
conform to any standard bus, but it's easy to glue to things. I
can also send you some simple projects for the DE1 board, which
should make for a nice exercise to port to the DE0 board (which
is quite similar in a lot of ways). I also have a peek/poke
unit entirely in Verilog using that same UART to do simple reads
and writes over Wishbone, which is the bus used by a lot of
OpenCores projects (and is nearly identical to Altera's Avalon
bus).
Is the static ram on the DE1 board easy to use?
- Dave
Ben.