1 Sep
2014
1 Sep
'14
3:09 p.m.
Hi Brent & all,
The board is loaded with 4116s for a total of 64K. It has the EX2 48K PROM
chip, and the DIP switches are currently set as you suggested (all ON) -
that's also the same setting I arrived at. I also reverted the cut & jump
changes discussed earlier, the ones related to clocking and using the board
in non-SD Systems enviros.
And yes, I too caught on to their particular use of terminology... banks
vs. pages vs. groups, etc. Did prove confusing for a few moments, though.
So then I decided to go on a fishing expedition... and hooked a single dead
74LS30, U19. That has now been replaced. I've also tested all of the
74LS00, 74LS02, 74LS10, 74LS20, 74LS14, 74LS244 and 74LS373 types, all are
fine. Then I got tired of testing chips.. I'll have to figure out the other
ones later.
Being pretty new to all this, I can tell you that reading datasheets and
devising tests for 74XX series ICs is a very good way to learn your way
around the world of digital logic - it's actually been a very helpful
series of learning exercises.. far better than listening to a lecture or
reading a textbook. Man am I glad I picked up & repaired that proto /
trainer chassis.. dang thing has really been coming in handy!
Do you have any idea who made/sold it? It's pretty similar in concept to a
Heathkit ET-3200, but way more versatile. Based on the workmanship (the
occasional lack of..) I think it was built by a student, probably as part
of a tech school course, or maybe a mail correspondence course? Either way,
it's a decent piece of equipment and it works great after going through it
- https://nerp.net/~legendre/altair/photos/proto-trainer.jpg
On Mon, Sep 1, 2014 at 3:16 PM, Brent Hilpert <hilpert at cs.ubc.ca> wrote:
On 2014-Aug-31, at 10:48 AM, drlegendre . wrote:
Couple of questions have come up..
While waiting for the new SRAM card to arrive, I thought I'd see what I
could learn about the SD Systems 'Expandoram II' DRAM card I currently
have. One major difference that I immediately noticed is the lack of a
block-address assignment feature. The JTM board allows the user to
arbitrarily map each of the (4) 4K groups to any 4K boundary in the
memory
space. But the SD card is organized into 4x 16K
groups, and each group
can
only be enabled or disabled.
Oddly, I can't find any info on the mapping scheme in the document. For
example, if only group 3 is enabled, where does it map? 0000-4000 or
C000-FFFF.. or elsewhere?
But here's my +real+ question.. the document has a section on operating
the
board in non-SD Systems environments, and that
would seem to apply, here.
They state that "Some CPU boards (they don't mention which) supply a
different phase of the system clock on pins 24 & 25. If one of these
boards
is used with the Expandoram II, make the
following changes...", and then
go
on to describe the changes - basic cut &
jumper stuff, two locations.
Does anyone know if this difference in clock signals is relevant to the
MITS 8080 CPU board? If the board isn't receiving the clock it expects,
it's no surprise that it seems to behave so badly, eh..? Perhaps just go
ahead and make the changes and give it a go? It's easy enough to revert
it,
if it doesn't help.
Lastly, I also discovered that the SD board had Wait State enabled.. and
the doc says that's only required for 4MHz CPU operation. The 8080A runs
at
2Mhz, so I've disabled the wait state. Not
sure if that was screwing
things
up as well, but +probably+ not - it would just
slow down the RAM access,
wouldn't it? Phantom was also enabled, and it's certainly not needed in
this instance, so I disabled that as well.
Any ideas on the mapping issue? Or more importantly, the clocking issue?
The mapping scheme is wrapped up in the on-board address-decoding PROM
chip.
It's 'described' in a rather cryptic table near the end of the manual.
It seems they intended the board for use in their own multi-user systems
and didn't feel the need
to document it thoroughly - the manual is a bit of an after-thought, like
the vague comment about the clocking.
It uses a slightly different scheme than that previously mentioned for
providing multiple 64K address spaces.
It looks like the idea was to have the upper 16 or 32K as common system
memory while
the lower 48/32 was swapped per user.
SDS is also using different nomenclature:
SDS bank == group (set of chips on board)
SDS page == bank (address space)
Is your board populated with 4116 chips for 64K total or some subset of
4164s?
Also, do you know whether your board has the '32K PROM' or the '48K
PROM'?
Assuming you have 4116s, cursory examination suggests the configuration
switches should be:
1 ON - enable all 4 on-board groups (SDS banks)
2 ON "
3 ON "
4 ON "
5 ON - this board is bank (SDS page) 0, with board
enabled after reset or POC
6 ON "
7 ON "
8 ON - turn on this board
If the board 'clear' jumper is set for POC rather than RESET, it will
require a good POC signal from the Altair to enable the board.
The board takes in the REFRESH signal from the S100 bus.
This is a non-standard signal that post-dates the Altair, intended to work
from the Z80 refresh facility to simplify use of DRAMs.
It's not clear why they use the signal, or whether it's actually required,
as it looks like all the refresh circuitry (address counter, etc) is on the
board.
Perhaps it was just to keep the refresh synchronized with other DRAM
boards.