Hardware vs Simh (and FPGA)

On Apr 24, 2013, at 10:27 PM, Jim Stephens <jws at jwsss.com> wrote: That's from Xilinx's new line that has a beefy ARM processor built into the chip which interfaces nicely to the FPGA logic. I don't know if you're likely to use that for a CPU project, though it's great for a lot of other things. The one that's on that board has approximately 3 times the FPGA logic that the DE0 has; if you really wanted to expand the FPGA logic for the same price, you could also try Terasic's DE2-115, which has more than twice the logic that Digilent board does (note that the Zedboard is only available to academic customers, and the DE0-115 has a lower price for academic customers). http://www.terasic.com.tw/cgi-bin/page/archive.pl?No=502 I like Terasic's boards a LOT, and the DE2-115 comes packed with a lot of REALLY nice features for hobbyists (it's like the DE0 on steroids). The Xilinx toolchain which includes the Zynq devices is freely available as well. http://www.xilinx.com/products/design-tools/ise-design-suite/ise-webpack.htm Xilinx has a new toolchain out called "Vivado", but it's VERY new, and therefore somewhat unpolished. I haven't used it yet, but I hear unfavorable things from some colleagues. Stick with ISE for now. Like Altera, it runs on Linux and Windows just about equally well. The 360/30 project calls for an FPGA of about the size used on the DE0; the "1000K gates" Spartan 3 has about 17K logic elements, while the DE0 has about 16k. Manufacturers stopped using the "gate count" nomenclature a while ago because it's not particularly accurate or useful, so an LE count is usually better. That's also a really old board, and Xilinx has EOLed the original Spartan-3 line (the Spartan-3A and -3E lines are alive and well still). FWIW, a brief primer on FPGA nomenclature, if you're going to be looking at sizes: A "logic cell" or "logic element" usually means a 4-input, 1-bit lookup table with a (bypassable) 1-bit output register. This can implement any 4-input logic function (basically as a truth table) and optionally register it. The bigger FPGAs (Arria/Stratix for Altera, Kintex/Virtex for Xilinx) have bigger LUTs to implement more complex features in a single logic element, but their sizes are usually given in an "equivalent" 4-input LUT count; for example, an EP2S60 is a Stratix II (2S) with the equivalent of 60K LEs. It's kind of a hand-wavy number, because they essentially just apply a scalar multiple to the actual number of larger elements they have, but in the general case it's a lot more useful than the "equivalent gate count" numbers from a decade ago. In any case, you should be able to fit the 360/30 FPGA on the DE0, though you'll have to create the project file and do the pin assignments yourself. You'll also have to hack out any Xilinx-specific things in the VHDL if there are any, which is usually just PLLs and block RAMs in most smaller projects (there are other things that might be lurking, but they'd be unlikely in a project this size). I don't know about the /65, though; that's on a much bigger FPGA that has 110K equivalent LEs, and it uses PCI Express to communicate with the host PC to run as the channel. It doesn't have sizing info, but that project would definitely need significant mods to work with smaller boards. It might be a fun (if somewhat advanced) project to port it to work on the Zynq, since the built- in ARM would provide the functionality of the channel emulator quite nicely. No guarantees on whether the 360/65 part of it would fit in the FPGA, though, since there's no sizing info provided on the page (you could always try to download and build it, though the free software won't build for a Virtex5 that big; if you're really curious, I could build it with mine, since I have access to the full suite). - Dave