7 Jun
2010
7 Jun
'10
3:36 p.m.
Keith wrote:
It terms of pure clock cycles per second, definitely.
Most FPGA eval
boards (and his in particular) run around 50mhz(ie come with onboard
50mhz oscillator).
Off by nine orders of magnitude. They commonly use 50 MHz.
This is for clocking the synchronous design. So the
flip flops are
driven by this clock. Most of these boards will accept upwards of
100mhz. There are some internal-to-the-FPGA processes that can run
~400mhz.
The flip-flops may be driven by the external clock input, but often this
is not the case. Almost all modern FPGAs contain either PLL or DLL
blocks that can be used to synthesize other clock frequencies from the
external input. On the FPGA eval boards with a 50 MHz oscillator, I
routinely run the flip-flops of my designs at frequencies up to 200 MHz.
My limited understanding is that most commercial
applications are less
than 250mhz because high speed designs are tough to troubleshoot.
Crosstalk, connectors, etc can all become big problems.
It can be difficult to
troubleshoot external interfaces at those speeds,
but it is not uncommon to run internal logic at those speeds and
external interfaces at lower speeds.
Eric