5 Oct
2012
5 Oct
'12
10:42 a.m.
From: Rob Doyle
Sent: Friday, October 05, 2012 12:48 AM
I think I noticed some differences to some of the Exec
Mode
instructions. I assume that those will need to be reconciled, also.
The I/O instructions, specifically, differ madly.
The KL-10 uses the I/O instruction model which was created for the
PDP-6, although it supports far fewer device types than the 166, KA,
or KI: <7><7 bit device code><3 bit op code><rest of
instruction>
The KS-10 uses a much simpler model, with different 9-bit opcodes (all
beginning with <7>) affecting different states of the machine. Because
the KS has a Unibus (yeah, PDP-11), the memory-model I/O is part of the
different instruction set.
With an FPGA, adding additional data paths later
probably won't be a
problem. I'm guessing that other things like memory and IO is going
drive the FPGA size - not the routing resources. No matter how they
are implemented, the additional page tables will require FPGA memory,
so I should probably plan on them.
Are you planning to put all of memory into the FPGA? Because the PDP-10
operating systems manipulate the page tables, so they need to be in main
memory.
Rich Alderson
Vintage Computing Sr. Systems Engineer
Vulcan, Inc.
505 5th Avenue S, Suite 900
Seattle, WA 98104
mailto:RichA at vulcan.com
mailto:RichA at LivingComputerMuseum.org
http://www.LivingComputerMuseum.org/