29 Nov
2016
29 Nov
'16
9:07 p.m.
On 11/29/2016 01:47 PM, Peter Coghlan wrote:
A single chip plus tranceivers solution would be ideal
but I couldn't see it
being that easy :-)
I have a single chip plus transceivers solution but my single chip is a
Xilinx Artix 7 FPGA. Maybe that's cheating but it does implement
register reads and writes, interrupt cycles, bus master operations, and
memory reads and writes in that single chip. :-)