16 Nov
2011
16 Nov
'11
6:44 p.m.
Chuck Guzis wrote:
Someone who wants to substitute, say, a CPLD for a
bunch of unclocked
TTL is going to have to come up with a clock--and then determine how
that will affect function.
I've had no problem with putting asynchronous logic into CPLDs, where
CPLD is defined as having a bunch of sum-of-products macrocells. (Some
vendors have, for marketing reasons, called some LUT-based devices CPLDs.)
Of course, if the asynchronous logic has dependencies on the specific
propagation delays of the original logic family used, that won't likely
work in a CPLD, but then, it won't likely work reliably when the vendor
of the logic family does a process shrink or any other change. Designs
that depend on the prop delays should generally be avoided, as they are
prone to terrible problems.
I've done a limited amount of asynchronous logic in Spartan-3 FPGAs.
Xilinx says don't do it, and the static timing analysis tool throws up
its hands, but with a little effort it seems possible to do it.
However, I wouldn't want the job of implementing a large async circuit
in an FPGA. Life's too short.
Eric