Pipelining and Dec Jupiter thoughts....

Speaking of ECL: DEC did some amazing work with ECL VLSI in the early 1990s. There was an R&D project called "BIPS" (for "billion instructions per second") -- which aimed to build a single-chip processor that would run at a gigahertz. That was way faster than the clock speeds of the time, and the notion was that to do this you needed to use ECL logic. But there wasn't any large scale integration with ECL, so DEC set out to create that. Part of the problem was that each ECL fab had its own design rules, and those fabs were a shaky business (not enough volume). That meant creating a CAD system which could adjust the design to a new set of design rules quickly. They built an interesting hybrid system where you could write the design partly as geometries (for things like memory cells), partly as transistors, partly as gates, and partly as C code. I remember an example, where they had a transistor schematic for a single-bit latch, and then wrapped it in a loop: "for (i=0; i < 64; i++) { <schematic> }". The magic was that (apart from the few bits of explicit geometry-level design) it was all parameterized, so they could regenerate the actual wafer geometry overnight for a new fab. The CAD system also allowed extracting a behavioral model from the design. The original plan, if I remember right, was to build an Alpha with this technology. That morphed into building a MIPS, and I think they might have gotten that to work. Another part of the puzzle was figuring out how to feed 100 watts of power to a chip, and get rid of that amount of heat, neither of which were anywhere close to what was done at the time. I still have some of the tech reports that describe that piece (and I contributed a wild idea -- which unfortunately DEC didn't get around to patenting before the project was shut down). paul