31 Aug
2009
31 Aug
'09
12:20 p.m.
Greetings all;
In my continued efforts to try and get my 11/34a functioning I decided to
set up my logic analyser and trap ALL of the 56 Unibus signal lines to see
if I could spot anything that was being held asserted when it shouldn't.
For reference, my 11/34a is set up like:
1 M8266 -------------------------------------------|
2 M8265 -------------------------------------------|
3 M9301 YJ-----| FLIPCHIP
4 M7856---------------------------|
5 National Semiconductor Memory Board--------------|
6 G7232---------|
7 G7232---------|
8 G7232---------|
9 M9302--------| G7232---------|
I only have the basic front-console, so not the lovely button-filled
operators console. All the NPR jumpers are in place. All voltages check
out.
The symptoms are:
Unit powers on, RUN light comes on and then quickly goes out. When the
BOOT/INIT switch is toggled, again, RUN light on, then out. Clearly the
unit is HALTing on something, but I can't work out what and nothing seems
to appear on the console.
When I analyse the bus the unit follows what, from the Unibus design
manual, appears to be a standard start-up procedure.
- All signals float (obviously)
- All signals cleared, DCLO/ACLO/INIT asserted
- 773000 is placed on the Address lines (as configured in the bootstrap)
- DCLO negates
- ACLO negates
- INIT negates, and then immediately:
- Address lines are cleared
- SACK is asserted
I find no mention of SACK being asserted in the Unibus manual in its
start-up section. Furthermore, as my understanding goes, SACK should only
I am pretty sure SACK should no0t be being asserted at this point.
be asserted when a bus master has accepted a grant and
is beginning a
transaction cycle. There is NO activity on the request/grant lines, so
nothing should be allowed to become bus master, so I think this SACK
signal should not be happening.
Where are you monitoring the grant lines? Remember they are not bussed,
they are daisy-chained from one slot to the next. So an open-circuit in
one of them may mean what you're seing on the logic analyser is not what
the boards are seeing.
The M9320 terminator (as has been stated here many times before) can
assert SACK. It asserts SACK if a grant gets all the way to the
terminator -- that is if no device intercepts the grant. Unfortunately an
open-circut grant line will have the same effect.
Try remoing the M9302 (on a Unibus this short you don't need to
terminate the far end for testing) and see what happens then.
-tony