Jules Richardson wrote:
Someone asked this over on the Sinclair group a short while ago, but I
suddenly thought that someone here might know...
Basically they were wondering what the internals of the Z80's
instruction fetch were, given that some instructions are multiple bytes
in length, but there's only a single-byte instruction register.
I theorised that control in the Z80 is all just a state machine, so
multiple instruction bytes presumably advance things to a new state (and
what's left in the IR during execution is just one byte from a
multi-byte instruction) - but it sounds like the OP was wondering if
anyone knew the exact mechanism (basically, has the design of the state
machine ever been documented anywhere).
(Given that I'm on a 'homebrew CPU' trip right now, I'm rather curious,
too :-)
Quite possibly this level of detail's never been made publicly
available, but I figure someone here may have had close involvement with
Zilog and know more. Online resources cover the overall internal
architecture, but just 'black box' the control logic section (including
the IR).
Rodnay Zaks had a fat Z80 book that went into quite some detail of the timing of the bus
and mentioned a hidden "W" register, but I don't recall what that was for --
holding a
byte temporarily during some do-si-do. I have the book but it is buried in the garage.
I have no doubt prefix bytes, (CB, ED, DD, FD) just set a flop that modify the
interpretation of subsequent fetches -- that is more economical than storing the entire
byte (or two bytes in some cases). Immediates and IX/IY offsets just go right to the
latch in front of the ALU.
I'll try and find the book.