8 Mar
2016
8 Mar
'16
8:58 p.m.
On Mar 8, 2016, at 12:44 PM, Mike Ross <tmfdmike at
gmail.com> wrote:
It will have 2 sets of configuration switches. One is the starting address
(on a 4KB boundary). The other is the number of 4KB blocks that the
board will respond to.
I may have a couple of other options like the speed at which it can
respond (the FRAMs have a 35 ns access time) and the size of the
IO hole.
I wrote the Verilog for the CPLD last night and as I finished it, I thought of
a few other options that might be useful. I?ll look it at some more once I?ve
done the simulation.
TTFN - Guy
No, it will only have 128KW. Since it?s a single FRAM part, I?m not going to
try and ?stock? different flavors (especially since I?ll be having the boards
assembled at the board house).
But you will do something to allow memory to be switched in and out? I
presume this thing wouldn't work in an 11/20 unless it was strapped
back to 32KW? Or will the 11/20 be happy and simply ignore the
unaddressable memory beyond 32KW?