1 Jan
2006
1 Jan
'06
9:53 a.m.
It appears to me that a lot of enginnering has now turned into some
high-level-theology: one just has to *believe* that the result is
correct - if not: hopefully find someone else to blame - of course:
mistakes in VHDL source code also exist.
I can attest to this : an obscure error in a tiny voiceband DSP I once
made took months of benchtime to debug. The error was traced back to a
typo in my VHDL code. The simulation testbench + firmware, as always,
did not trigger the condition....
Jos Dreesen