Hi,
Anyone interested ? Unit is in Paris, France. Disk may have been formated.
If you need only some parts, it'll maybe be possible. Don't ask me anything
about this machine, I din't have it handy, but there are many ressources on
the web.
Salut!
St?phane
http://DECpicted.blogspot.com
Shannon Spurling writes:
> I have this old IBM system. I think I identified the CPU as an 8085.
> The motherboard/ card cage looks like the one from the Datamaster. Thing
> is, I can't find ANY info on it. It's a four piece system with a tower,
> monitor, keyboard and printer. The tower is huge, and has dual 8"
> floppies.
Do the tower and printer look anything like the stuff in the background
on
http://www-03.ibm.com/ibm/history/exhibits/pc/pc_9.html
According to the text this was a configuration where "two workstations
... permitted two people to use the system simultaneously", and maybe
the unit you have is the non-workstation component of the system (shared
printer access, maybe shared file access?)
Some of the keypunch-to-floppy units IBM sold in the 70's seemed to
me to be vaguely styled like the Datamaster. Maybe these also inspired
the Heath-Zenith 89.
Tim.
Anyone know a good place to source a DSSI Terminator (DEC part no
12-31281-01), ideally in the UK? All I can find is dealers who won't publish
a price. There are none on eBay either.
Regards
Rob
ZDNet a mainstream media company looked at VCF UK. It showed British-micro
history. Very interesting...could have had more commentary! Great pictures
though.
Murray--
Does anyone have a photo of a GEC Campus Packet Switch Exchange (aka
CPSE)? It's an X25 switch circa mid-80s, popular in UK Universities,
and we need a photo for a book. No offer refused; credit will be given!
--
Pete Peter Turnbull
Network Manager
University of York
On Sat, Jun 19, 2010 at 1:18 PM, Zane H. Healy <healyzh at aracnet.com> wrote:
> Now for an interesting bit of info. ?Apparently there are two different
> types of Firmware. ?One for the PDP-11, and one for VAXen. I'll see if I can
> get a little bit more info on that.
Given that the RFM (Resident Firmware Menu) which provides the setup,
autoconfiguration and diagnostics, runs natively on the host (via the
boot DU 253 shortcut), then the machine specific ROM needs the
compatible machine code, so did they release a version with VAX
machine code perhaps?
> Now for the important part, the whole manual.
> http://www.avanthar.com/~healyzh/RQZX1.pdf
Excellent, thank you for providing. It confirms what everyone has said
so far about the supported drive-set and dual-support (MSCP and
TMSCP).
One interesting note I found in the RSTS/E 9.7 release notes is this comment:
{AA-NB17A-TC} 4.3.3 TMSCP Tape Driver If your system contains only one
TMSCP tape drive (TU81 or TK50), you must designate it unit
0....elided...
NOTE The controller number must also match the drive number.
I wonder if this applies to MSCP side for disks too?
I have been offline with other distractions for a few weeks but I hope
to get back to exploring the problem booting soon.
I have this old IBM system. I think I identified the CPU as an 8085.
The motherboard/ card cage looks like the one from the Datamaster. Thing
is, I can't find ANY info on it. It's a four piece system with a tower,
monitor, keyboard and printer. The tower is huge, and has dual 8"
floppies. If I were to guess, I would presume it was a version of the
Datamaster, but I can't find any thing that states this thing was ever
made. The number on the tag says 5324, and it is IBM. Any one have info
or someplace to look? And, if it is possible, I would really like to get
my hands on some tech/repair info.
>>> Don't know if this has been posted here yet, but Don Maslin's widow
... And for anyone who is wondering -- Sellam was (is) already working
with one of the Maslin family's grown children about archives.
I have an old 286 computer i use for tasks that won't run on a newer maching... My old printer is dead and when trying to connect a new printer it doesn't work...? What can i do to get the newer printers like lexmark to go with the old 286 HP VECTRA???? TNX
Eric Smith <eric at brouhaha.com> wrote:
> Johnny Billquist wrote:
> > But if we call this an 11/74, what shall we call the 11/70 with CIS?
>
> I wrote:
> > Fantasy? There wasn't such a thing, since there wasn't an 11/70 with a
> > KB11-E CPU that was necessary to accomodate the KE74-A CIS.
>
> Johnny wrote:
> > Then you are saying that Don North's work on the CIS microcode
> > for the 11/74 is a figment of his imagination?
>
> Not at all. I'm saying that it wasn't an 11/70, and that no 11/70 had
> CIS. He seems to agree with me.
Excellent. :-)
So let's call that an 11/74 then, as I've been doing the whole time.
Then the question is, what do we call the 11/70 with modifications to be
able to run multiprocessor configurations?
Johnny
Hi guys,
I've got a Laserjet III laser scanner module kicking around in my
junkbox, harvested from an utterly screwed LJ3. It has a fibre-optic
light pipe on one side, which connects to a photosensor on the
motherboard. Does anyone know what the frequency or period of the
photocell signal is?
That is to say, how long does it take for the scanner to make one
complete pass from "horizontal blank" to the right margin -- in other
words, the time from the leading edge of one photocell pulse to the next?
I'm toying with the idea of repurposing the scanner module for another
project (using a BluRay laser diode to print directly onto photographic
paper then process using a 3-bath B&W process), and I'd like to figure
out (in advance!) what the requirements will be placed on the paper
drive system (among other things!)
Thanks,
--
Phil.
philpem at philpem.me.uk
http://www.philpem.me.uk/
Eric Smith <eric at brouhaha.com> wrote:
> Johnny Billquist wrote:
>> Another way to name them would perhaps be:
>>
>> KB11-B - Old 11/70 CPU with synch FPP.
>> KB11-C - New 11/70 CPU with asynch FPP.
>> KB11-CM - MP modified KB11-C
>> KB11-E(?) - The new 11/74 CPU with asynch FPP and CIS.
>>
>> I seem to remember reading somewhere that the 11/74 CPU were to be
>> called KB11-E, but I also have this nagging feeling that KB11-E might
>> have been the 11/44, or possibly the 11/60.
>
> The 11/44 CPU was a KD11-Z. The 11/60 CPU was a KD11-K.
That might be correct.
>> Now, as I myself pointed out, RSX regards the 11/70mP as an 11/74, and
>> that is also what the CPU identification code in RSX calls it.
>
> Since the 11/70mp and 11/74 were never official products, there was a
> lot of conflation of the designations. Without the optional CIS,
> software can't easily distinguish an 11/70mp from an 11/74, so it
> probably simply didn't bother to try. Thus whether software reports the
> CPU as an 11/70mp or an 11/74 doesn't really prove much of anything.
Indeed. Which I think I tried pointing out.
>> But if we call this an 11/74, what shall we call the 11/70 with CIS?
>
> Fantasy? There wasn't such a thing, since there wasn't an 11/70 with a
> KB11-E CPU that was necessary to accomodate the KE74-A CIS.
Then you are saying that Don North's work on the CIS microcode for the
11/74 is a figment of his imagination? And the results they got back
>from running performance tests on this hardware?
I think it's just easier, for this discussion, to call that the 11/74,
and call the multiprocessor PDP-11s that went out to field test, and
which also were kept running inside DEC until not long ago, 11/70mP.
Mind you - just for this discussion.
Otherwise I'm just happy to keep calling CASTOR:: an 11/74, just as my
emulated 11/74 (MIM::), which also don't have CIS...
Johnny
> At 8:49 PM -0400 7/1/10, Bryan Pope wrote:
>> Another great item for sale from my collection:
>>
>> http://cgi.ebay.com/ws/eBayISAPI.dll?ViewItem&item=190412195573
I know it says different ROM version in your auction description, but
how exactly does this model differ from the Educator 64 (one of which
is also up on ebay at the moment?)
--
jht
allison <ajp166 at verizon.net> wrote:
> On 06/30/2010 11:27 AM, Johnny Billquist wrote:
>> > I'll reply to this one last time, and then I'll give up.
(I can't seem to keep out, can I? :-) )
> I can't add too much to this regarding what parts and what DEC
> designators applied
> but here are memories of the time frame.
>
> The first multiprocessor 11/70 was built with existing hardware and a few
> wire wrap and jumper mods. Memory said there were 4 total, three inside DEC
> and one at CMU that they hacked together possibly with DEC help.
CMU did multiprocessor PDP-11s before DEC did, I think. However, they
went about it differently than the 11/74 (or whatever you want to call
it). Search for C.MMP and similar stuff on the net for more information
about CMUs multiprocessor PDP-11 projects.
The 11/74 systems were designed and built inhouse, although they might
have talked with CMU to get help, experience and whatnot. Reportedly
more than three systems were built. Rumors have it that they even had
some systems out to external customers for test, but all systems were
returned at the end of the tests (even though there is a persistent
rumor about Ontario Hydro keeping their).
I think I know of/heard of three systems that were in use inside DEC
long after the system was officially cancelled. We had, of course,
CASTOR:: which was the RSX engineering system, and which was up and
running as late as 2002 (2005?) or so. This was a 4-CPU system.
Then we had POLLUX::, which I think was a 2-CPU system. Not sure, but I
think it might have been DECnet engineering who had it. The third I've
heard about is PHEANX:: which might have been POLLUX:: after a move to
field service, and possibly also using bits and pieces from other
places inside DEC.
As far as I know, all of these systems, as well as the ones gone out on
field test, were KB11-CM cpus. So, no CIS option ever made it out of
prototypes, nor any KB11-E.
The boards from the 11/74 systems that were returned were allegedly used
in plain 11/70 machines inside DEC afterwards. They were, after all,
plug compatible with the normal 11/70 systems. The KB11-E boards would
not have been that, though.
> It
> would evolve
> to a design project to make that buildable as marketing felt they could
> sell it.
> However at the same time VAX/11/780 was real and also the various product
> groups were feeling the effects of FCCs new class A and B limits for
> RFI/EMI.
> That and the high end market had been moving to more addressable memory
> for bigger datasets and computationally wider data words as the tasks were
> getting bigger. At that time the big calculations that were important were
> atomic physics and weather models and both were associated with massive
> [by that eras measure] datasets. In many respects the same pressures
> repeated
> themselves in the 32bit to 64bit evolution [Alpha].
Indeed. But looking at the papers on the 11/74, their aim was more
towards high availability. Thus the total redundancy in the system, as
well as the ability to bring CPUs and memory on- and offline while the
system is running, and even run diagnostics on one CPU while the others
were serving. Even going as far as being able to physically remove
hardware from a running system.
So, high performance and large memory applications were not the target
of the 11/74. In fact, a 4 CPU 11/74 had about three times the
performance of an 11/70, but that was only aggregated performance. A
single task ran no faster on an 11/74 than on an 11/70. Possibly slower.
The question I think DEC asked itself wether there would be more point
in just selling four 11/70 machines to the customer, or one 11/74. And
four 11/70 won.
I know that RFI/EMI became a problem around this time. I think that
originally DEC planned to stop the 11/70 because of this, but since it
was such a popular machine, and no real replacement existed for quite a
while (the VAX was not a good enough replacement for an 11/70 in some
applications, mostly realtime), they were eventually forced to redesign
the 11/70, and that is where the DEC Datasystem 570 came from.
So the 11/70 in the corporate cabinet was ok with regards to RFI/EMI
radiation, while the older style full height (H960?) cabinets are not.
Or at least that is my understanding.
> It was my understanding that the 11/70 continued as a grandfathered
> EMI and the new multiple cpu died due to EMI issues (plethora of cables
> and multiple racks) and it was a faster number cruncher than VAX-11/780.
> The VAX had higher potential as the new reigning super minicomputer. It
> wasn't long after that I'd seen a VAX-11/782, 785 and VAXclusters.
The long cables from multiple CPUs to the memory boxes might have been
an problem with RFI/EMI in an 11/74, I don't know. But the 11/74
machines I have seen in pictures have been in the newer corporate
cabinets, which would imply that they were designed to pass the RFI/EMI
requirements.
> There were several of the PDP11 flavors that would die or morph as a
> result of manufacturing and serviceability issues.
I bet. :-)
Johnny
Don't know if this has been posted here yet, but Don Maslin's widow,
Winnie, died on 12/15/09. Here is the obit:
"Bristol Maslin "Winnie" (1928-2009)
Bristol "Winnie" Maslin died peacefully at her home in La Jolla on
Christmas night, Dec. 25, 2009. Winnie was a long time resident of San
Diego and La Jolla. She was an active member of The La Jolla Villagers
and the Social Service League of La Jolla, Darlington House.
Winnie was born on April 7, 1928, to Mary and Bristol Moore in
Bardwell, Kentucky. Her family moved to Toledo, Ohio, where she grew
up. She graduated from Scott High School in Toledo. Winnie came to San
Diego as a young woman where she had a long career at Fireman's Fund
Insurance as an Underwriter. She is preceded in death by her husband
of 45 years, Donald Maslin, the love of her life. Her life with Don
was full and exciting as they traveled the world and enjoyed many
wonderful experiences together. They had many close friends as well,
with whom they shared their life. With no children of their own, they
were especially close to her sister's family in San Diego.
Winnie is survived by her sister and brother-in-law, Ann and Hal Heist
of San Diego; nieces, Deborah Sharpe and Dawn Thompson of San Diego;
nephew, David Heist of Livermore, Ca.; and many grandnieces and
nephews. She had an especially close friendship with her only sibling,
Ann. The family will greatly miss our sweet aunt who enjoyed life,
parties, laughter, family and friends.
Winnie's ashes will be scattered at sea where her husband Don's were
scattered five years ago. They are together again. A celebration of
Winnie's life will be held on Sunday, Jan. 10, at her beloved home in
La Jolla, overlooking the beauty of the La Jolla Shores."
Here is the link:
http://www.legacy.com/obituaries/signonsandiego/obituary.aspx?n=bristo
l-maslin-winnie&pid=138344556
Checked the real property database for San Diego county and it doesn't
appear that the house has sold yet.
I can share addresses and some phone numbers of the family offline if
anyone wants to try and initiate contact. Best bet might be nephew
David Heist of Livermore, CA, former owner of Hoptown Brewery. Who
lives in Livermor - Sellam?
-W
Forwarded from the rescue list...these are a favorite of mine but
unfortunately I am unable to retrieve them. Hope someone does!
---------- Forwarded message ----------
From: Bill Green <bill at supposedly.org>
Date: Thu, Jul 1, 2010 at 4:06 PM
Subject: [rescue] Fwd: Sun3 machines in Scranton PA
To: rescue at sunhelp.org
Hello,
I just saw the below on comp.sys.sun.hardware. It doesn't look like
it's been posted here.
----------------------
From: billg999 at cs.uofs.edu (Bill Gunshannon)
Newsgroups: comp.sys.sun.hardware
Subject: Sun 3's for rescue
Date: 22 Jun 2010 19:08:40 GMT
Anybody here close enough to travel to Scranton, PA interested in saving
a couple of Sun3 Ddeskside pedestels from the landfill?
Might have some stuff shortly and trying to line up a way to keep them
alive for at least a little while longer.
bill
--
Bill Gunshannon ? ? ? ? ?| ?de-moc-ra-cy (di mok' ra see) n. ?Three wolves
billg999 at cs.scranton.edu | ?and a sheep voting on what's for dinner.
University of Scranton ? |
Scranton, Pennsylvania ? | ? ? ? ? #include <std.disclaimer.h>
_______________________________________________
rescue list - http://www.sunhelp.org/mailman/listinfo/rescue
> The same with MO drives probably holds. I may still have a Pinnacle
> Apex 4.3GB drive here somewhere. In addition to being somewhat
> delicate, it was very expensive when compared to a standard IDE
> drive.
> I don't consider the later cheap removable-media drives like Zip,
> Jaz, Sparq... to be in the same reliability category as the
> Bernoullis. It's a shame that the technology was abandoned.
MO drives still have a few holdouts, in the worlds radiology and graphic arts. But CD-R and DVD-R have come to dominate even in those holdout areas.
In the radiology world variants on the RT-11 filesystem are still found today on MO drives, although the data hasn't passed through a real PDP-11 in decades.
Tim.
Jules,
A while ago you posted that you had the manual and discs for a Compaq
SLT/286. Do you by chance still have them? If so does it include the
Supplemental Programs disc?
Thanks
James
"Shoppa, Tim" <tshoppa at wmata.com> wrote:
> "Walter F.J. Mueller" <w.f.j.mueller at gsi.de> wrote:
>>> Johnny Billquist <bqt at softjar.se> wrote:
>>> > I wasn't aware that any prototypes ever were produced and came as
>>> > far as being functional. I thought it was just paper work that
>>> > had bee done.
>>>
>>> The 11/74 wasn't marketed, as pointed out in this thread, but a
>>> few systems were build by DEC. A picture of such 11/74 system
>>> was made available by Tim Shoppa, see
>>>
>>> http://www.trailing-edge.com/~shoppa/1174Xopen.jpg
>>>
>>> You'll nicely see the four CPUs.
>
>> Yes, I know of these systems. However, that is not an 11/74 on that
>> picture, but an 11/70mP. There is a difference...
>> As pointed out, the 11/70mP was marketed as an 11/74, but it's a
>> different CPU.
>
>> The easiest way to see that this is a picture of an 11/70mP is by
>> looking at the lower rotary switch, which only have four positions, and
>> not eight (which the 11/74 have). So no CIS on this machine.
>
>> The only 11/74 picture I've seen so far is the silk screen panel picture
>> posted a few days ago. Unfortunately I've already forgotten the name
>> (I'm lousy with names, sorry) of the person who posted it, and who also
>> worked on the 11/74 CIS microcode.
>
>> The machine on that picture is probably CASTOR:: by the way.
>
> The people who work with/maintain CASTOR:: call it a 11/74, FWIW.
Yes, I know.
I'll reply to this one last time, and then I'll give up.
Don North reported that he had been a part of the team that had written
the CIS microcode for the 11/74 CPU.
I commented that I thought the 11/74 CPU had only been a paper product.
Don North also pointed out that marketing "stole" the 11/74 moniker for
the 11/70mP system.
Now, throughout this discussion, we need some way of separating what we
are talking about. DEC internal project papers seems like a good start.
There we have the 11/70mP, which is a modified 11/70 with just the
addition of the ASRB cache bypass and memory interlock, as well as the
cache bypass bit in the PDR, and a cache bypass bit and flush control in
the cache control CSR.
The 11/74 is a total redesign of the 11/70 CPU, with the same
modifications as the 11/70mP, but also the addition of the CIS, removal
of one Massbus, and redesign of a whole bunch of CPU boards, including
removing one clock signal not used, and the addition of new clock
signals and control signals required by the CIS.
I'm only talking CPUs here, not systems.
Another way to name them would perhaps be:
KB11-B - Old 11/70 CPU with synch FPP.
KB11-C - New 11/70 CPU with asynch FPP.
KB11-CM - MP modified KB11-C
KB11-E(?) - The new 11/74 CPU with asynch FPP and CIS.
I seem to remember reading somewhere that the 11/74 CPU were to be
called KB11-E, but I also have this nagging feeling that KB11-E might
have been the 11/44, or possibly the 11/60.
Now, as I myself pointed out, RSX regards the 11/70mP as an 11/74, and
that is also what the CPU identification code in RSX calls it.
But if we call this an 11/74, what shall we call the 11/70 with CIS?
So, for the purpose of this thread, I decided to go with Don Norths
naming, and call the 11/70 modified for multiprocessor operations the
11/70mP. If you look at the picture on your site, Tim, you'll also
notice that the text on the front panel actually says something like
"PDP-11/74 MP". (Not sure about the /74, but you definitely see the "MP"
part. (http://www.trailing-edge.com/~shoppa/1174Xopen.jpg)
Now, compare that to Don Norths picture of the 11/74 front panel:
http://www.ak6dn.com/stuff/1174.jpg.
> They never used the term "11/70mP" in front of me for sure. I would occasionally elicit comments about multiprocessing on 73's or 93's but it always came back to "our 11/74 does it THIS WAY" because that was the working example.
I'm not disagreeing with you, Tim. I'm just trying to point out that we
have two different CPUs here, one of which I thought was never made, but
Don actually claims that it did exist, even if just as one prototype.
The system was called an 11/74 everywhere, but for the purpose of this
discussion, we need to make a distinction between the CPUs.
> I'm not saying that "11/70mP" is wrong, indeed it's used in some of the drawings and memos to describe what was commonly called the 11/74.
Yes.
> CIS was real important to some DECcies circa late 70's for some Cobol requirement but coming from the real-time side none of us ever cared. We'd just run across machines that had this unneeded option.
Indeed. And the 11/70 don't have it, nor does the 11/74 systems that
ever were used.
CASTOR:: was 4 CPUs, by the way, while PHEANX:: was only 2, if I
remember right.
Johnny
Hello all,
This is just a short email to let the West Australian members know that
the Artifactory, Perth's very own Hackerspace (in the correct sense of
the word), has started hosting a regular, fortnightly event called
'Classic Computing Appreciation Night'. Several of our current members
have at least a passing interest in collecting, restoring and setting up
classic computers; as this event is being run in conjunction with our
'Circuit Hacking Mondays', there should also be at least one or two
people around to help with the troubleshooting and repair of your
favourite micro- or mini-computer.
The space's electronics facilities include several soldering stations
and CROs, PAL/SECAM/NTSC and analogue RGB monitors, a logic analyser and
an (E)EPROM programmer. Depending on the demand, there may also be a PC
capable of reading from, and writing to, most common 3.5" and 5.25"
floppy disk and tape formats; we also have a fairly respectable
collection of OS installation kits for many DEC, SUN, HP, SGI, IBM
RS/6000, Apple, Commodore and Amiga systems. And for the particularly
adventurous, the space also has a home-designed and built CNC milling
machine and a RepRap 3D printer that could be used to machine or
(literally) print replacement parts and panels.
The space is located in Mount Lawley, and all are welcome. Advice and
ideas are free; workshop use is free for members of the hackerspace, or
$10 waged/$5 unwaged. See
http://wiki.artifactory.org.au/doku.php?id=projects:classiccmp for more
details of the event, and http://hackerspaces.org and
http://en.wikipedia.org/wiki/Hackerspace for information about the
hackerspace movement in general.
Hope to see some of you there,
Peter
On JMon, 28 Jun 2010 22:15:57 +0100, Philip Pemberton <classiccmp at philpem.me.uk> wrote:
Having played with a the Canon II printer series scanners (the guts of both the Laserjet II and Apple Laserwriter II), some comments:
> Well, working backwards from DPI and print speed gives about 3MHz dot clock:
>
> 300DPI * 11 inches (paper height) * 3ppm = 9900 lines per minute
> (thus, the line rate is 9900Hz, or 9.9kHz)
> 9900lpm * 300 dots per line = 2.97e6
> (thus, the pixel rate is 2.97MHz)
Unless you are using the control board, the above calculation is moot: the scanner is a DC brushless motor - the speed is controlled by the input voltage. The control board closes a motor loop based on the feedback optical pulse and synchroniz(s)es the speed with the shift register clock. You can chose a clock rate to suit your system, build the motor control loop with a D/A, and set up logic to fire off at the right time based on the feedback optical pulse. If you are using the control board, all you have to do is feed the data in and the board will take care of the bit clocking. If you are generating the bit clock, you can determine your DPI. The II series uses a 6-sided mirror.
> Replacing the laser assembly might be "interesting", as will realigning
> the optics. My back-of-an-envelope calculations suggest I need a 0.085mm
> spot size to get to 300DPI:
>
> 300dpi = 300 dots per inch, or 1/300in per pixel
> 1/300 * 25.4mm/in = 0.0846667
>
> Focusing that will be.... "fun", especially with a 20mW blue diode
> laser... and I need to find a beam sensor that's sensitive to blue light.
The sensor on the board should work if you remove the red filter/attenuator on the input to the fibre optic cable. You might have to either increase the gain of the amp at the detector or place an attenuator in the optical chain. In any case, you should replace the red filter with a suitable pass filter to match your laser.
IIRC the laser is collimated to the desired spot size, i.e. the beam is parallel through the optical path - no focusing per se. However, going from red to blue will change the deflection characteristics of the optical path. You will probably see a narrower page at the same distance from the folding mirror and possibly some non-linearities. By changing the distance from the final mirror you should be able to control the page width. Non-linearities are a different matter.
>
> Seems like it should work... though designing a suitable
> constant-current controller with ~3MHz analog current modulation will be
> interesting. PWM would require ~768MHz modulation, so analog is the
> "easy way out", and beam power is roughly linear from the lasing
> threshold (30mA) up to 10mW (~40mA). Hmmm.
As mentioned above, you will have to control the motor voltage to sync with the bit oscillator to achieve the DPI. Also note that most laser diodes have a photodiode as part of the assembly and power is also in a control loop.
[...]
> So am I right in thinking it has some form of PLL to generate the pixel
> clock from the beam-detect (or motor tacho?) pulses?
Actually, you probably want to fix the bit rate (crystal oscillator) and control the motor speed so that you get n bit counts between laser pulses. It should be fairly easy to control to +/- 1 bit. Note that the number of bits will be greater than the dots you wish to generate in order to take care of margins.
>
> That's along the lines of what I was going to do... lock a fairly
> slow-loop PLL off the either the beam detect or the tacho (haven't
> decided which), then use the pulses from that to drive the clock input
> for the data shifter.
>
> It's like the CX-VDO all over again.... :)
Different problem...
>
> --
> Phil.
> classiccmp at philpem.me.uk
> http://www.philpem.me.uk/
I used two scanners a few year ago to make a far IR scanner. The first was a modified mirror wheel which slow scanned the vertical and the second was the horizontal scan. The optical output was fed to pyroelectric detector found in a motion detector with modified electronics. Fun toys.
CRC
> From: "Chuck Guzis" <cclist at sydex.com>
> Not all Northstar diskettes are HS. One of the models (Advantage?)
> isn't--and it's that format that the Microsolutions MatchPoint will
> read, not the others. It's been too long since I've seen the darned
> things...
I think the machine you are thinking of might be the N* Dimension. The Advantage
still uses 10-sector floppies.
I've never seen the Dimension but vintagemicros on Ebay was selling one a while
back and had a picture of it. Apparently it was MS-DOS compatible.
RodSmallwood" <rodsmallwood at btconnect.com> wrote:
> How difficult would it be to extend one of these FGPA PDP-11's to be put
> on a quad DEC board and be a plug in replacement for say an 11/93 or
> 11/94 CPU. (M8981-AA OR 11/91-BA)?
>
> Rod
Hi Rod,
possible and feasible, but requires three tasks to be addressed:
1. an adapter board is needed to connect the FPGA development
boards (holding the FPGA and memory) to the UNIBUS or QBUS.
Main active part of this adapter board are the bus transceiver
for UNIBUS or QBUS.
2. The UNIBUS or QBUS bus interface logic can be added to the
FPGA. Given that the system clock period is small compared
to typical times of these buses it is quite simple and
straight forward to implement such a bus interface.
3. the current w11a implementation doesn't support bus masters
on the I/O bus. DMA transfers from disk/tape devices are
currently emulated. Next versions of the FPGA implementation
however will add this functionality.
But keep in mind: the current FPGA implementation isn't tremendously
faster than a J11.
Walter
everyone gather round. No hard woods, only wiffle ball bats :)
anyone own/used to own 1? In the rare event someone has one or more toasted units, and willing to part with them, I'm interested. There's more then one way to skin a cat (PERISH THE THOUGHT!).
I'm off topic but I know there are a lot of laser printer enthusiests
here and hopefully someone that has been digilent about the firmware
for this printer... not to mention people who like fixing things.
Has anyone possibly kept older firmware versions for this printer around?
I have a Magicolor 2550 that I have been running for several years.
It always had a problem where it would fall off my network and I would
have to power cycle it to recover. Didn't matter if DHCP or static IP
was used... the ethernet would just go dead.
A few months ago, I decided to "fix" this and went looking for a
firmware upgrade. My firmware was orginal and there was a newer one,
many revisions advanced. So, I reflashed the printer. This fixed the
network problem however in trade, I got two new worse problems. Now,
the image on the paper is slightly rotated... about 5 degrees so that it
is no longer square to the paper. Additionally, the front panel keypad no
longer functions and if you press any key, the printer enters into a loop,
printing a menu page and you have to power cycle it to recover. Nice.
I absolutely put in the correct firmware for this printer model so Konica
apparently has some issues.
I've gotten no response from Konica support and so I am looking for someone
who may have archived older versions of firmware so that I can revert the
thing to something less hostile.
It was otherwise a really nice color laser printer and I _should_ have just
lived with the network problem.
Again, it's a Magicolor 2550EN. Not the "DN" model which does use a different
firmware image.
Thanks and I appreciate off-topic bandwidth.
Chris
--
Chris Elmquist
"Walter F.J. Mueller" <w.f.j.mueller at gsi.de> wrote:
>> Johnny Billquist <bqt at softjar.se> wrote:
>> > I wasn't aware that any prototypes ever were produced and came as
>> > far as being functional. I thought it was just paper work that
>> > had bee done.
>>
>> The 11/74 wasn't marketed, as pointed out in this thread, but a
>> few systems were build by DEC. A picture of such 11/74 system
>> was made available by Tim Shoppa, see
>>
>> http://www.trailing-edge.com/~shoppa/1174Xopen.jpg
>>
>> You'll nicely see the four CPUs.
> Yes, I know of these systems. However, that is not an 11/74 on that
> picture, but an 11/70mP. There is a difference...
> As pointed out, the 11/70mP was marketed as an 11/74, but it's a
> different CPU.
> The easiest way to see that this is a picture of an 11/70mP is by
> looking at the lower rotary switch, which only have four positions, and
> not eight (which the 11/74 have). So no CIS on this machine.
> The only 11/74 picture I've seen so far is the silk screen panel picture
> posted a few days ago. Unfortunately I've already forgotten the name
> (I'm lousy with names, sorry) of the person who posted it, and who also
> worked on the 11/74 CIS microcode.
> The machine on that picture is probably CASTOR:: by the way.
The people who work with/maintain CASTOR:: call it a 11/74, FWIW.
They never used the term "11/70mP" in front of me for sure. I would occasionally elicit comments about multiprocessing on 73's or 93's but it always came back to "our 11/74 does it THIS WAY" because that was the working example.
I'm not saying that "11/70mP" is wrong, indeed it's used in some of the drawings and memos to describe what was commonly called the 11/74.
CIS was real important to some DECcies circa late 70's for some Cobol requirement but coming from the real-time side none of us ever cared. We'd just run across machines that had this unneeded option.
Tim.
Item number:300434169483 (9 boards @ USD10 + postage each)
AT-GPIB/TNT+. IEEE 488.2 (ISA)
Single-Board GPIB Interface and Analyzer
I think the analyzer software that runs on Windows 95/98 and ME is
bundled with the 1.70 version driver that may be available by request
(from the 2nd URL)
http://joule.ni.com/nidu/cds/view/p/id/532/lang/enhttp://www.ni.com/support/gpib/drivers/
I have run a similar card in a Compaq DeskPro 6500? P3 PCI machine with
a legacy ISA slot (captured an HP150 boot sequence).
As I read it the HPDrive software will run on Window 95/98, ME with this
board. See the HPDrive site.
http://www.hp9845.net/9845/projects/hpdrive/
(... sending this from the correct FROM address would help...)
Hi guys,
I've got a Laserjet III laser scanner module kicking around in my
junkbox, harvested from an utterly screwed LJ3. It has a fibre-optic
light pipe on one side, which connects to a photosensor on the
motherboard. Does anyone know what the frequency or period of the
photocell signal is?
That is to say, how long does it take for the scanner to make one
complete pass from "horizontal blank" to the right margin -- in other
words, the time from the leading edge of one photocell pulse to the next?
I'm toying with the idea of repurposing the scanner module for another
project (using a BluRay laser diode to print directly onto photographic
paper then process using a 3-bath B&W process), and I'd like to figure
out (in advance!) what the requirements will be placed on the paper
drive system (among other things!)
Thanks,
--
Phil.
classiccmp at philpem.me.uk
http://www.philpem.me.uk/
"Walter F.J. Mueller" <w.f.j.mueller at gsi.de> wrote:
> Johnny Billquist <bqt at softjar.se> wrote:
> > I wasn't aware that any prototypes ever were produced and came as
> > far as being functional. I thought it was just paper work that
> > had bee done.
>
> The 11/74 wasn't marketed, as pointed out in this thread, but a
> few systems were build by DEC. A picture of such 11/74 system
> was made available by Tim Shoppa, see
>
> http://www.trailing-edge.com/~shoppa/1174Xopen.jpg
>
> You'll nicely see the four CPUs.
Yes, I know of these systems. However, that is not an 11/74 on that
picture, but an 11/70mP. There is a difference...
As pointed out, the 11/70mP was marketed as an 11/74, but it's a
different CPU.
The easiest way to see that this is a picture of an 11/70mP is by
looking at the lower rotary switch, which only have four positions, and
not eight (which the 11/74 have). So no CIS on this machine.
The only 11/74 picture I've seen so far is the silk screen panel picture
posted a few days ago. Unfortunately I've already forgotten the name
(I'm lousy with names, sorry) of the person who posted it, and who also
worked on the 11/74 CIS microcode.
The machine on that picture is probably CASTOR:: by the way.
> arcarlini at iee.org wrote:
> > I've read somewhere that it [PDP-11/74] was full of flat ribbon
> > cables and would have been a beast to maintain.
>
> Well, you see on the picture that there was quite a bit of
> flat ribbon cables :).
Yes, when you run multiple CPU configurations, you do get many flat cables.
However, if you were to run the 11/74 in a single CPU configuration, it
would not have had more flat cables than an 11/70. So it seems strange
if that would have been the reason for cancelling it.
On the other hand, I think that CIS never was popular, or in any demand,
for the PDP-11, so if that (and multiprocess capability) was the only
things the 11/74 brought to the table to differ it from tne 11/70, then
I can understand why they would cancel it if they had problems with the
multiprocessor part.
> The 'PDP 11/70 Multiprocessor Technical Manual (Preliminary Version)'
> is on bitsavers, see
>
> http://www.bitsavers.org/pdf/dec/pdp11/1174/EK-70MP-TM_PRE_1170mp_Prelim_Te…
>
> and gives you a feeling of the modules and interconnects.
Yes. And all evidence I ever see is that the only systems DEC actually
did get working was the 11/70mP. That they actually got the 11/74 (CPU)
beyond paperwork was what was news to me.
> Johnny Billquist <bqt at softjar.se> wrote
> > You do know that the J11 is already designed for mP usage, except that
> > DECs testing of that was even more secret than the 11/74?
>
> Sure, the mP instructions WRTLCK and the TSTSET of the J11 are
> documented, and allow cleaner way to implement spin locks than
> the 'asrb hack' of the 11/74. In a future version of the w11a I'll
> probably also implement the instructions supported by 11/34 and
> J11 and make the 'processor profile' selectable at start time, much
> like in the simh simulator.
That would be nice. While RSX don't use it, you could use it for Unix,
or other systems.
The J11 also have the cache bypass bit in the PDR, btw.
What instructions are you thinking about when you say 11/34 btw?
> > But FPP is among the most important things in there as well, I'd say.
> > Lots of software who won't be happy without it.
>
> That's true from a performance point of view. However
> - you can run RSX and Fortran without FPP (did this 30 years ago
> when the FPP broke on the 11/45 I was working with...).
True. But you cannot run almost anything else. I don't think I've seen
any other language that do not require the FPP.
> - you can run 2.11BSD without FPP (I'm doing that each time I
> boot 2.11BSD).
Yes, that was fixed recently, right?
> So a FPP is very good to have, but not my highest priority. Also,
> it's quite a project to design, implement and verify it, with the
> verification, as usual, being the most time consuming part.
True.
> > By the way. You don't have to worry about cache coherency. The
> > PDP-11/74 do not do that. Cache coherency is managed by software
> > on the PDP-11 (well, in RSX, since that's the only system that
> > supports the hardware). In short, the real hardware do not implement
> > any sort of cache coherency in hardware.
>
> I know, but I'll go for a cache with full cache coherency. That will
> make it a lot easier to try a MP hack for 2.11BSD. And RSX, if I ever
> get to it, will not mind.
True. Definitely will not break anything. But it will make your life
more complicated. :-)
> Johnny Billquist <bqt at softjar.se> wrote:
> > Good thinking.
> > But I'm surprised by some numbers here. The J11 at 20 MHz is
> > only slightly faster than an 11/70. In fact, if you can throw
> > the 11/70 into running all from cache, it might even be slightly
> > faster than an 11/9x.
> > Or so I seem to remember from looking at the numbers back when
> > I last was digging into this.
> >
> > Maybe I'm mixing some numbers up here... What I do remember for
> > sure is that the 11/9x machines run at 20 MHz, and that they are
> > not more than maybe 1.2 times the speed of an 11/70 in general.
>
> oops, you are right, I was mixing numbers here and forgot about
> a factor of four. Here the revised arguments:
>
> See http://www.village.org/pdp11/faq.pages/prfmnc.html , there
> is a table comparing 11/70 with various J11 systems:
>
> 11/23 11/53 11/73 11/83 11/93
> ----- ----- ----- ----- -----
> CPU F-11 J-11 J-11 J-11 J-11
> Microcycle(ns) 300 267 267 222 222
> Clock (MHz) ? 15 15 18 18
> Performance 0.2 0.5 0.7 1.2 1.4
> (11/70 = 1)
> Cache no no yes yes no
> Floating-Pt opt no no yes yes
> Coprocessor
>
> My mistake was to forget that the J11 needs 4 clock cycles per
> microcycle (MC), that's why 18 MHz clock leads to 222 ns MC period.
>
> In the end the J11 (222ns MC) is faster than the 11/70 (150 ns MC)
> because it has a better micro architecture (three stage pipeline
> vs. instruction prefetch only). The J11 is roughly a factor two
> better compared to 11/70 in terms of MC efficiency.
Hmm, I seem to remember checking numbers a while ago and came to the
conclusion that if the 11/70 would have all memory as cache, it would
outperform the J11. Atleast at 18MHz, maybe also 20MHz.
(Btw, that table is slightly wrong, as the 11/9x eventually made it to
20MHz).
I have a processor handbook which gives instruction speeds of 11/70
instructions with cache hits and without, which tells you how fast the
machine would be if you were all cache. The 11/70 suffers because memory
is so slow.
Johnny
Johnny Billquist <bqt at softjar.se> wrote:
>>..
>> "Walter F.J. Mueller" <w.f.j.mueller at gsi.de> wrote:
>> At some later time maybe I'll try a really fast design, with separate
>> instruction and data caches and significantly more parallelism than
>> the J11 had.
> Hmm. I wonder if that might cause headaches? There might be code out
> there that require your i-cache and d-cache to be consistent with each
> other.
sure, there is self modifying code. The maindec zkdjb2 for example has
a sequence like
mov #000240,(pc)
jmp (r1)
and tests that the 'nop' was executed and not the 'jmp'. However, the
cache, even separate i-d, is only one aspect, main point is to get
all the different 'write-after-read' hazards in the pipeline under
control. That's why I stayed with a simple 'prefetch-only' 11/70-like
implementation in the first round. Even in that case one has to be
careful and suppress for example the prefetch when the destination is
pc. Otherwise a 'clr pc',often found at the end of primary bootstraps,
will not do a 'jmp @#000000' but execute the opcode after the 'clr pc'.
Walter
Hello,
Since I need to make some more space here, the following systems are
for sale. Location is The Netherlands, I can ship internationally
(probably expensive), delivery in the southern part of the UK in early
August might also be possble.
HP9000/300 double-height enclosure (IIRC this was a 317, I'll have to
check).
HP-HIl audio extension 46081A
HP-HIL Mouse + keyboard
HP 7958 hpib disk
IEM HP-IB mass storage unit with 2 3.5" floppy drives
HP-IB cables + documentation
HP9000/310 with keyboard and mouse
and also some other stuff for sale:
Philips PC200 (rebadged grid XT laptop), power supply is broken but it
will also work on DC
IBM 43p/140: 332MHz processor, 256MB ram and 9GB disk
with regards,
Michiel
Johnny Billquist <bqt at softjar.se> wrote:
> Good thinking.
> But I'm surprised by some numbers here. The J11 at 20 MHz is
> only slightly faster than an 11/70. In fact, if you can throw
> the 11/70 into running all from cache, it might even be slightly
> faster than an 11/9x.
> Or so I seem to remember from looking at the numbers back when
> I last was digging into this.
>
> Maybe I'm mixing some numbers up here... What I do remember for
> sure is that the 11/9x machines run at 20 MHz, and that they are
> not more than maybe 1.2 times the speed of an 11/70 in general.
oops, you are right, I was mixing numbers here and forgot about
a factor of four. Here the revised arguments:
See http://www.village.org/pdp11/faq.pages/prfmnc.html , there
is a table comparing 11/70 with various J11 systems:
11/23 11/53 11/73 11/83 11/93
----- ----- ----- ----- -----
CPU F-11 J-11 J-11 J-11 J-11
Microcycle(ns) 300 267 267 222 222
Clock (MHz) ? 15 15 18 18
Performance 0.2 0.5 0.7 1.2 1.4
(11/70 = 1)
Cache no no yes yes no
Floating-Pt opt no no yes yes
Coprocessor
My mistake was to forget that the J11 needs 4 clock cycles per
microcycle (MC), that's why 18 MHz clock leads to 222 ns MC period.
In the end the J11 (222ns MC) is faster than the 11/70 (150 ns MC)
because it has a better micro architecture (three stage pipeline
vs. instruction prefetch only). The J11 is roughly a factor two
better compared to 11/70 in terms of MC efficiency.
The w11a on the other side does one microcycle per clock cycle. So
one can expect that is roughly a factor 5.5 faster than a 18 MHz J11
(MC rate is 11 times higher (50/4.5), but J11 has a factor two better
MC efficiency).
Let's look at the Dhrystone benchmarks again:
w11a 11500 lps
11/53 830 lps
So the w11a is measured to be ~14 faster than a 11/53. The 11/53
has half the performance of a 11/70, so one expects that the w11a
is about a factor 7 faster than a 11/70. Because w11a and 11/70
have a similar micro architecture that should match the MC rate,
and indeed it does (50/6.7). So the numbers are consistent, finally.
Thanks for pointing that out.
Walter
Johnny Billquist <bqt at softjar.se> wrote
> You do know that the J11 is already designed for mP usage, except that
> DECs testing of that was even more secret than the 11/74?
Sure, the mP instructions WRTLCK and the TSTSET of the J11 are
documented, and allow cleaner way to implement spin locks than
the 'asrb hack' of the 11/74. In a future version of the w11a I'll
probably also implement the instructions supported by 11/34 and
J11 and make the 'processor profile' selectable at start time, much
like in the simh simulator.
> But FPP is among the most important things in there as well, I'd say.
> Lots of software who won't be happy without it.
That's true from a performance point of view. However
- you can run RSX and Fortran without FPP (did this 30 years ago
when the FPP broke on the 11/45 I was working with...).
- you can run 2.11BSD without FPP (I'm doing that each time I
boot 2.11BSD).
So a FPP is very good to have, but not my highest priority. Also,
it's quite a project to design, implement and verify it, with the
verification, as usual, being the most time consuming part.
> By the way. You don't have to worry about cache coherency. The
> PDP-11/74 do not do that. Cache coherency is managed by software
> on the PDP-11 (well, in RSX, since that's the only system that
> supports the hardware). In short, the real hardware do not implement
> any sort of cache coherency in hardware.
I know, but I'll go for a cache with full cache coherency. That will
make it a lot easier to try a MP hack for 2.11BSD. And RSX, if I ever
get to it, will not mind.
Walter
Johnny Billquist <bqt at softjar.se> wrote:
> I wasn't aware that any prototypes ever were produced and came as
> far as being functional. I thought it was just paper work that
> had bee done.
The 11/74 wasn't marketed, as pointed out in this thread, but a
few systems were build by DEC. A picture of such 11/74 system
was made available by Tim Shoppa, see
http://www.trailing-edge.com/~shoppa/1174Xopen.jpg
You'll nicely see the four CPUs.
arcarlini at iee.org wrote:
> I've read somewhere that it [PDP-11/74] was full of flat ribbon
> cables and would have been a beast to maintain.
Well, you see on the picture that there was quite a bit of
flat ribbon cables :).
The 'PDP 11/70 Multiprocessor Technical Manual (Preliminary Version)'
is on bitsavers, see
http://www.bitsavers.org/pdf/dec/pdp11/1174/EK-70MP-TM_PRE_1170mp_Prelim_Te…
and gives you a feeling of the modules and interconnects.
Walter
Hi, Walter.
"Walter F.J. Mueller" <w.f.j.mueller at gsi.de> wrote:
> Johnny Billquist <bqt at softjar.se> wrote:
> > > "Walter F.J. Mueller" <W.F.J.Mueller at gsi.de> wrote:
> > > I've also implemented a PDP-11 on an FPGA. It is a full 11/70 with
> > > split I&D, MMU and cache. No FPP so far. Available peripherals are so
> > > far DL11, LP11, KW11L, PC11, and RK11. All I/O is channeled over via
> > > 'remote-register-interface' onto a single bi-directional byte stream
> > > interface, so the FPGA board needs a backend PC with a server program
> > > to handle the I/O requests.
>
> > Any plans on the FPP? It would be really nice and useful to have.
>
> Hi Johnny,
>
> sure, an FPP is on the 'todo-list', but it doesn't have the highest
> priority. After having put the first version on OpenCores I'd like to
> add a trace/debug unit (allowing hardware breakpoints ect), and add
> a few more peripherals, especially larger disks. Currently I have
> only an RK11 controller, good enough for proof-of-principle, but
> not enough for real usage.
Disks are definitely a good thing. And as usual, I'll advocate MSCP.
Even though it's not the simplest, it's simply just the best. :-)
But FPP is among the most important things in there as well, I'd say.
Lots of software who won't be happy without it.
> > As for traps and double errors, feel free to ask. I don't know if I have
> > all the answers, but I might be able to figure them out. Besides, I also
> > have access to one (or three) functional 11/70 machines.
>
> I've tested much of the implementation against simh and xxdp's, but there
> are still a few loose ends regarding corner cases. It be great to run a
> few test programs on simh, a real 11/70, and my fpga implementation,
> called now w11a.
Feel free to talk with me more offlist, and we can see when we can
schedule some testing on real hardware.
> > The 11/53 is a really slow machine. Not that helpful to compare with. But you
> > seem to push a nice number anyway. But 50MHz... The J11 in an 11/9x machine
> > runs at 20 MHz, which would suggest that you should only be able to push about
> > 2.5 times the performance, unless you do some more clever tricks.
> > (The 11/9x machine runs all memory as cache.)
>
> I know, but the 11/53 is the only pdp-11 where I know the Unix Benchmark
> and thus the Dhrystone results, so it became the reference.
>
> Even though my implementation is quite different from the organization of
> the original 11/70, it has essentially the same instruction timing as a
> 11/45 or 11/70 when expressed in clock cycles. The 11/45 or 11/70 CPU's
> ran with a 150 ns clock period (ignoring clock stretching here), thus a
> 6.7 MHz clock. A register-register operation takes 2 cycles, a
> "mov r0,(r1)+" for example 5 cycles.
>
> Because the cpi (cycles-per-instruction) for 11/70 and the w11a is very
> similar and both have a good cache the w11a should simply be 50/6.7 or a
> factor 7.5 faster than a 11/70.
>
> The 11/70 and the w11a have some pipelining, instruction fetch and
> decode/operate can overlap for register destination instructions. The
> J11 is more pipelined, here fetch, decode, and operate stage can overlap.
> Therefore register-register instructions take 1 cycle in the best case,
> a "mov r0,(r1)+" for example 3 cycles.
>
> Therefore a 50 MHz w11a will not be 2.5 times faster than a 20 MHz J11,
> maybe just 1.5 times faster. The w11a is intentionally implemented in a
> quite simple and conservative way, prime goal was to get it right and
> working, and not to get it fast.
Good thinking.
But I'm surprised by some numbers here.
The J11 at 20 MHz is only slightly faster than an 11/70. In fact, if you
can throw the 11/70 into running all from cache, it might even be
slightly faster than an 11/9x.
Or so I seem to remember from looking at the numbers back when I last
was digging into this.
Maybe I'm mixing some numbers up here... What I do remember for sure is
that the 11/9x machines run at 20 MHz, and that they are not more than
maybe 1.2 times the speed of an 11/70 in general.
> At some later time maybe I'll try a really fast design, with separate
> instruction and data caches and significantly more parallelism than
> the J11 had.
Hmm. I wonder if that might cause headaches? There might be code out
there that require your i-cache and d-cache to be consistent with each
other.
> > IIST is needed for RSX to be happy (the only OS that supports the 11/74),
> > and you also need to implement parts of the memory bus behaviour with
> > interlocking. You can ignore the MK11 box CSRs, even though it will look
> > a little funny, but you do need separate DL11s for each CPU core, along with
> > the rest of the I/O bus, or else things will probably not work. The 11/74
> > is a shared memory machine, but not shared I/O bus.
>
> I'm fully aware of this, the MP version will have one I/O bus per CPU and
> a shared memory and asrb interlock, and caches with proper cache coherency.
Yes. But what I was thinking of was the fact that at a level below this,
you have the CPU that be issuing read-modify-write cycles to memory, and
those needs to be interlocked to memory.
At a higher level, the 11/70 was modified for asrb to always bypass
cache, and then you had two other ways to bypass cache as well. But
bypassing cache is only half the problem, as you also need to make sure
some memory operations are atomic, as seen from other cpus.
But if you know a thing or two about cpu and memory design (which it
would appear you do), then you probably understand the problem already.
By the way. You don't have to worry about cache coherency. The PDP-11/74
do not do that. Cache coherency is managed by software on the PDP-11
(well, in RSX, since that's the only system that supports the hardware).
In short, the real hardware do not implement any sort of cache coherency
in hardware.
> It's true that RSX is the only OS that supports an 11/74. Unfortunately I
> don't have an RSX11-M plus license. So the plan is to patch 2.11BSD to support
> an MP system. Sounds like a long shot, but looking into the kernel sources
> I concluded that a funneling or 'big kernel lock' type MP support seems to
> be quite feasible. Will not scale well, but for a 'dual-core' this is likely
> good enough.
It's definitely doable. However, it is not that simple.
The reason why DEC choose RSX as the OS for implementing multi-processor
support is that it does not, in general, use interrupt priority levels
to serialize access to data, protect sections of code, or implement locks.
Unix do. So, in short, everywhere where the interrupt priority is
changed, you potentially need to change the code, since another
processor might still get interrupts at that level, and do things you
thought you had locked out.
But I see your problem. It would be great if we could solve the
situation with RSX at some point...
Johnny
>> 140420130808
> Looks like a 5ESS ate it, from the other material for sale in this lot.
They all seem to have Dilog CU160's. What was the CU160? Disk, communications?
My bet is the seller was once one of the Boston-area DEC used equipment dealer of the 70's/80's, who is now into Telecom instead.
Let's see, in the late 80's: American Used Computer was already pass? (wasn't he in Boston?). ELI was big. Who else was there? I used to know all the names by heart. There were several who weren't as big as ELI but still worthwhile.
Tim.
Item number:140420111955
If someone in Europe would be interested I should like to arrange it to get
one. Of course the price is high but It allows to make an offer.
Sergio
2010/6/15 Jim Stephens <jws at jwsss.com>
> Does anyone have some Prodos and or other software for one of these? My
> supply is locked up, and I don't know if I ever had Prodos.
>
> The system I'm getting had its prodos floppy stepped on by a misque long
> ago, and it was overwritten, so at a minimum I would appreciate that.
>
> I could send the damaged disk and let you overwrite at my expense as an
> alternative if media is a problem, or I can dig for some blanks in my pile.
>
> thanks
> Jim
>
I've got a Xytronic 137ESD
(http://www.howardelectronics.com/xytronic/137ESD.html).
Which of these tips, keeping in mind I have the 137ESD, would be
appropriate for surface mount work?
http://www.howardelectronics.com/xytronic/tips.html
What temperature should I be set at for soldering? The number 630F
comes to mind, but I'm not sure.
What type of solder? I think I'm using 63/37, I think .015 OD.
Should I use flux? In what form? A pen? A syringe? A brush?
Any other standard accessories that might help?
Thanks
Keith
Does anyone have some Prodos and or other software for one of these? My
supply is locked up, and I don't know if I ever had Prodos.
The system I'm getting had its prodos floppy stepped on by a misque long
ago, and it was overwritten, so at a minimum I would appreciate that.
I could send the damaged disk and let you overwrite at my expense as an
alternative if media is a problem, or I can dig for some blanks in my pile.
thanks
Jim
Johnny Billquist <bqt at softjar.se> wrote:
> > "Walter F.J. Mueller" <W.F.J.Mueller at gsi.de> wrote:
> > I've also implemented a PDP-11 on an FPGA. It is a full 11/70 with
> > split I&D, MMU and cache. No FPP so far. Available peripherals are so
> > far DL11, LP11, KW11L, PC11, and RK11. All I/O is channeled over via
> > 'remote-register-interface' onto a single bi-directional byte stream
> > interface, so the FPGA board needs a backend PC with a server program
> > to handle the I/O requests.
> Any plans on the FPP? It would be really nice and useful to have.
Hi Johnny,
sure, an FPP is on the 'todo-list', but it doesn't have the highest
priority. After having put the first version on OpenCores I'd like to
add a trace/debug unit (allowing hardware breakpoints ect), and add
a few more peripherals, especially larger disks. Currently I have
only an RK11 controller, good enough for proof-of-principle, but
not enough for real usage.
> As for traps and double errors, feel free to ask. I don't know if I have
> all the answers, but I might be able to figure them out. Besides, I also
> have access to one (or three) functional 11/70 machines.
I've tested much of the implementation against simh and xxdp's, but there
are still a few loose ends regarding corner cases. It be great to run a
few test programs on simh, a real 11/70, and my fpga implementation,
called now w11a.
> The 11/53 is a really slow machine. Not that helpful to compare with. But you
> seem to push a nice number anyway. But 50MHz... The J11 in an 11/9x machine
> runs at 20 MHz, which would suggest that you should only be able to push about
> 2.5 times the performance, unless you do some more clever tricks.
> (The 11/9x machine runs all memory as cache.)
I know, but the 11/53 is the only pdp-11 where I know the Unix Benchmark
and thus the Dhrystone results, so it became the reference.
Even though my implementation is quite different from the organization of
the original 11/70, it has essentially the same instruction timing as a
11/45 or 11/70 when expressed in clock cycles. The 11/45 or 11/70 CPU's
ran with a 150 ns clock period (ignoring clock stretching here), thus a
6.7 MHz clock. A register-register operation takes 2 cycles, a
"mov r0,(r1)+" for example 5 cycles.
Because the cpi (cycles-per-instruction) for 11/70 and the w11a is very
similar and both have a good cache the w11a should simply be 50/6.7 or a
factor 7.5 faster than a 11/70.
The 11/70 and the w11a have some pipelining, instruction fetch and
decode/operate can overlap for register destination instructions. The
J11 is more pipelined, here fetch, decode, and operate stage can overlap.
Therefore register-register instructions take 1 cycle in the best case,
a "mov r0,(r1)+" for example 3 cycles.
Therefore a 50 MHz w11a will not be 2.5 times faster than a 20 MHz J11,
maybe just 1.5 times faster. The w11a is intentionally implemented in a
quite simple and conservative way, prime goal was to get it right and
working, and not to get it fast.
At some later time maybe I'll try a really fast design, with separate
instruction and data caches and significantly more parallelism than
the J11 had.
> IIST is needed for RSX to be happy (the only OS that supports the 11/74),
> and you also need to implement parts of the memory bus behaviour with
> interlocking. You can ignore the MK11 box CSRs, even though it will look
> a little funny, but you do need separate DL11s for each CPU core, along with
> the rest of the I/O bus, or else things will probably not work. The 11/74
> is a shared memory machine, but not shared I/O bus.
I'm fully aware of this, the MP version will have one I/O bus per CPU and
a shared memory and asrb interlock, and caches with proper cache coherency.
It's true that RSX is the only OS that supports an 11/74. Unfortunately I
don't have an RSX11-M plus license. So the plan is to patch 2.11BSD to support
an MP system. Sounds like a long shot, but looking into the kernel sources
I concluded that a funneling or 'big kernel lock' type MP support seems to
be quite feasible. Will not scale well, but for a 'dual-core' this is likely
good enough.
Walter
Hello Everybody,
Does anybody happen to have the contents of the PDP-11 boot/diagnostics
proms 23-248F1 & 23-616F1 available in SIMH loader format?
These are the proms on the M9312 boot/termination card.
Thanks,
Ed
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