test-drb June 2010

test-drb@ccmp.vtda.org

167 participants
232 discussions

need a k/b or 2 for a DEC Rainbow, and docs/warez for a Canon VP3000

by chrism3667＠yahoo.com

obtained 2 rainbows last night. The only k/b we could find in the guy's basement had a CTITOAH (or whatever the hell) designation, although it looked exactly like a R* k/b. I didn't argue the point. I now have 1 k/b between 3 R*s. Haven't cracked the veep open yet. I imagine it has a z80 or something monotonous like that. I'll screech if it has an 8088/8086, but I truly doubt it. Text is blue, strange, but was told it's a mono monitor. Need anything anyone can provide for it. Thanks.

14 years, 6 months

partial P112 kits

by marvin＠west.net

Wrong tools is sometimes just an excuse. I routinely solder SMD chips with .025" pin spacing with a soldering iron with about a 3/32" tip. Granted it is not my first choice, but my other iron died, and I'll use what I have. Since it works, I don't have a lot of incentive to buy the proper sized tip even though it makes soldering a LOT easier. My first choice would be a Metcal with a proper sized tip! And if I were in better shape financially and/or project wise, I'd take the complete P112 kit just for the fun of soldering the SMD components in place. Marvin >> The P112 looks pretty interesting. I'd consider a partial kit >> depending on the price. While I have successfully soldered one SMT >> part (the FTDI chip on the X0xb0x board), it wasn't fun and I would >> probably like to try to avoid having to do it again. I think I just >> lucked out that I didn't fry the chip. I bridged a number of pins >> and had to clean up with solder wick. > > Wrong tools. Betcha anything. > > -Dave

14 years, 6 months

H9281 wanted

by jdr_use＠bluewin.ch

If anyone has spare H9281 ( 4 or 8 slots ) that they would not mind selling off, I'd be interested. Jos Dreesen

14 years, 6 months

yet another pdp-8 in a fpga, but this time running tss/8 --> yet another pdp-11 in fgpa

by W.F.J.Mueller＠gsi.de

Hi there, Brad Parker just posted about his FPGA implementation of a PDP-11, which boots so far RT-11, RSTS V4, BSD 2.9 and Unix V6. There was a question how fast an FPGA solution might be compared to a PDP-11/93. I've also implemented a PDP-11 on an FPGA. It is a full 11/70 with split I&D, MMU and cache. No FPP so far. Available peripherals are so far DL11, LP11, KW11L, PC11, and RK11. All I/O is channeled over via 'remote-register-interface' onto a single bi-directional byte stream interface, so the FPGA board needs a backend PC with a server program to handle the I/O requests. The design is FPGA proven, runs on Digilent S3 and NEXYS2 boards, the former with 1 MB 10 ns SRAM, the later with 16 MB 70ns PSDRAM. Resource consumption is S3 board xc3s1000 2471 slices or 33% NEXYS2 board xc3s1200e 2624 slices or 30% The implementation was verified against many XXDP maindec's. There are some open issues, especially some details of trap and double error handling aren't correct yet. In practice this is of little importance, the FPGA system happily boots and runs BSD 2.11, a system using 22bit addressing and split I&D space. {Note: you need patch 447 for 2.11BSD to get FPP emulation and RK support working} On Performance: The design runs at 50 MHz. I've run parts of the Byte Unix benchmark on the FPGA systems. Given that the FPP is only emulated by the 2.11BSD kernel it makes only sense to look at the integer benchmarks. The Dhrystone benchmark 'dhry2reg' gives about '11500 lps' on both boards. For comparison see Michael Schneiders page http://www.vaxcluster.de/mambo/bench2.php?mach=pdp11 which gives about '830 lps' for a 11/53. There is little Dhrystone difference between the two boards despite the very different memory access times. The 8 kB cache with 32 bit cache lines really helps on the NEXYS2 board. I'm in the middle of homogenizing some internal interfaces and of some code cleanup, also the backend handler needs a re-write in C++ (currently perl). When that's done I'll make the whole package (VHDL sources, test benches, backend) available on 'OpenCores'. Finally a comment to Dave Mitton's remark > Now what would be really cool would be to make 4 CPUs and re-create > an 11/74 quad. > http://www.miim.com/faq/hardware/multipro.html#castor The reason why I picked a 11/70 and not a J11 as target is because my goal is a 11/74. I've implemented the IIST already and tested against the IIST Diagnostic I could find in XXDP (riiab0). A dual core will fit into a single xc3s1200e of the NEXYS2 board. The work needed is quite clear and doable (changes on cache, mmu, and cpu core for asrb). However, I've no plans to implement the CIS, so it will always be a subset of a 11/74. But for sure fun to do and run. With best regards, Walter

14 years, 6 months

Off-Topic: Old Phones...

by feedle＠feedle.net

Heya. Given the penchant of people on this list to collect all sorts of obsolete and antique tech, I figured I'd throw a query out here. I live in an old apartment block that has a 1920's vintage Western Electric intercom system. The system is in need of some "help" (it still works, but is far from what you'd consider 'optimal'). I'm a phone guy by trade, and would love to spend some of my personal time making this system work like it did when it was installed in 1927. If anybody out there has any knowledge of antique intercom systems like this, please E-mail me off list. I can provide more information (like pictures of the equipment and a better description). Just don't want to further dive down this rabbit hole on this list. For that matter, if there's a discussion list relevant to antique telephone systems, referring me there would be appreciated as well.

14 years, 6 months

Software-based floppy disc data separator

by classiccmp＠philpem.me.uk

Hi guys, Here's something for you lot to play with. It's a software implementation of the "Phase Jerked Loop" data separator, in C++ (although most of the logic is C), complete with notes... This is extremely sub-optimal, but "It Works For Me"... :) Tests against the old "Helix" decoder engine (the "smart" histogram analyser that really is anything but) are still ongoing. As a bare minimum, the timing figures need to be optimised -- most timesteps will end up with no accompanying state change. If you can eliminate some of these timesteps, you can speed up the code quite a bit. The catch is that the timestep must be a multiple of NSECS_PER_PLLCK/2, NSECS_PER_PLLCK and NSECS_PER_ACQ... The optimal value should be lcm(NSECS_PER_PLLCK/2, NSECS_PER_ACQ) [lcm = lowest common multiple]. Optimising the timing factors for a given acq-clock is likely to be the hardest part of the whole process... I'm willing to bet it'll work with data grabbed from a Catweasel, but I don't have any test data to play with... so that's left as an exercise to the reader. mfmbits is a vector<bool> which starts out empty and contains the output MFM bits after the loop has run. A sync marker will appear in mfmbits as 0x4489. buf is either an array or a vector containing integers of any sane size. These represent the timing values in units of Tacq (Tacq = 1/Facq, the frequency at which the acquisition counter is incremented). buflen is the length of this buffer. License is GPLv2, code is copyrighted to me. If you want to use this in closed-source software, email me and ask for a less restrictive licence. I'm getting pretty pissed off with people in the floppy disc preservation/analysis field keeping their toys to themselves (*cough* SPS), and have no intention of contributing further to such nonsense. > /** > * This is a software implementation of Jim Thompson's Phase-Jerked Loop > * design, available from AnalogInnovations.com as the PDF file > * "FloppyDataExtractor.pdf". > * > * This consists of: > * A data synchroniser which forces RD_DATA to be active for 2 clock cycles. > * A counter which increments constantly while the PLL is running, and is > * reset to zero on an incoming data bit. > * Whenever the counter reaches half of its maximum value, a > * new data window is started. > */ > > // Nanoseconds counters. Increment once per loop or "virtual" nanosecond > unsigned long nsecs1 = 0, nsecs2=0; > // Number of nanoseconds per acq tick -- (1/freq)*1e9. This is valid for 40MHz. > const unsigned long NSECS_PER_ACQ = 25; > // Number of nanoseconds per PLLCK tick -- (1/16e6)*1e9. 16MHz. > // This should be the reciprocal of 32 times the data rate in kbps, multiplied > // by 1e9 to get the time in nanoseconds. > const unsigned long NSECS_PER_PLLCK = 125/2; > // Number of clock increments per loop (timing granularity) > const unsigned long TIMER_INCREMENT = 1; > // Maximum value of the PJL counter. Determines the granularity of phase changes. > const unsigned char PJL_COUNTER_MAX = 16; > > // Iterator for data buffer > size_t i = 0; > > // True if RD_DATA was high in this clock cycle > bool rd_latch = false; > // Same but only active for 2Tcy (SHAPED_DATA) > int shaped_data = 0; > > // Phase Jerked Loop counter > unsigned char pjl_shifter = 0; > > // data window > unsigned char data_window = 0; > > #ifdef VCD > FILE *vcd = fopen("values.vcd", "wt"); > fprintf(vcd, "$version DiscFerret Analyser D2/DPLL 0.1 $end\n" > "$timescale 1 ns $end\n" > "$var reg 1 * clock $end\n" > "$var reg 1 ' pll_clock $end\n" > "$var reg 1 ! rd_data $end\n" > "$var reg 1 %% rd_data_latched $end\n" > "$var reg 1 ^ shaped_data $end\n" > "$var reg 8 & pjl_shifter $end\n" > "$var reg 1 ( data_window $end\n" > "$upscope $end\n" > "$enddefinitions $end\n" > "$dumpall\n" > "0*\n" > "0'\n" > "0!\n" > "0%%\n" > "0^\n" > "b00000000 &\n" > "0(\n" > "$end\n" > ); > #endif > do { > // Increment counters > nsecs1 += TIMER_INCREMENT; > nsecs2 += TIMER_INCREMENT; > > // Loop 1 -- floppy disc read channel > if (nsecs1 >= (buf[i] * NSECS_PER_ACQ)) { > // Flux transition. Set the read latches. > rd_latch = true; > shaped_data = 2; > > // Update nanoseconds counter for read channel, retain error factor > nsecs1 -= (buf[i] * NSECS_PER_ACQ); > > // Update buffer position > i++; > } > > // Loop 2 -- DPLL channel > if (nsecs2 >= NSECS_PER_PLLCK) { > // Update nanoseconds counter for PLL, retain error factor > nsecs2 -= NSECS_PER_PLLCK; > > // PJL loop > if (shaped_data > 0) { > pjl_shifter = 0; > } else { > // increment shifter > pjl_shifter = (pjl_shifter + 1) % PJL_COUNTER_MAX; > } > > // DWIN detect > if (pjl_shifter == (PJL_COUNTER_MAX / 2)) { > // Data window toggle. Latch the current RD_LATCH blob into the output buffer. > mfmbits.push_back(rd_latch); > // Clear the data latch ready for the next data window. > rd_latch = false; > // Update DWIN > data_window ^= 0x01; > } > > // Update shaped-data time counter > if (shaped_data > 0) shaped_data--; > } > } while (i < buflen); > > printf("mfmbits count = %lu\n", mfmbits.size()); -- Phil. classiccmp at philpem.me.uk http://www.philpem.me.uk/

14 years, 6 months

"The Paper" PET newsletter

by silent700＠gmail.com

Did anyone win this on ebay today? http://cgi.ebay.com/ws/eBayISAPI.dll?ViewItem&item=320547974650&ssPageName=… If so, do you plan on scanning it? If you scan, I will host. If you can't scan it and want me to, I will do so and send it back. -- jht

14 years, 6 months

FFS: SGI IP10 (Iris 4D) motherboard

by silent700＠gmail.com

The condition is unknown (other than not cracked and not rusty,) the box looks original, the RAM slots are empty, the ROM chips are labeled Boot 0 - Boot3, the zip code is 60074. Anyone want it? -- silent700.blogspot.com Retrocomputing and collecting in the Chicago area: http://chiclassiccomp.org

14 years, 6 months

Coleco ADAM Con - Montreal

by c.murray.mccullough＠gmail.com

Hi Everyone, A classic computer of the 8-bit era, the Coleco ADAM, is celebrated by all Adamites of Canada and the U.S.A., each year is winding up in Montreal, our 22 annual convention. The central part in my opinion is how to run an ADAM emulator on the PC. For those who still have a working ADAM, more power to you all. Happy classic computing! Murray :)

14 years, 6 months

joining cctalk

by dgriffi＠cs.csubak.edu

I referred someone to this mailing list, but he's unable to join. The server says that he needs to wait to be approved, but nothing happens. -- David Griffith dgriffi at cs.csubak.edu A: Because it fouls the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing in e-mail?

14 years, 6 months

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test-drb June 2010