While reading an old resume, I came across something I forgot about. I
used to admin some 3Com 3+ and 3+/Open systems. 3Com made the hardware
(beefed up PC stuff) and wrote or owned the OS.
Anybody know what became of 3+/Open?
-James
James Fogg
JD Fogg Technology Consulting
18 Watershed Lane
Wilmot, NH 03287
(603) 724-2243
www.jdfogg.com
I found one of the rom images I put up was a bad prom. Another one read
consistently but didn't match two other sources. The images have been
replaced. Affected images : 752A9, 248F1, 616F1. I replaced them after
getting multiple other images and comparing, so I'm confident the ones up
now are all correct.
I'd like to post source listings for the boot programs. Anyone got a program
to re-arrange the bits correctly, then disassemble?
Jay
The 6800 indeed had HCF and while I forget the opcode
(not a regular 6800 user) it was real. Basically if
the opcode was encountered the chip executed bus cycles
and did nothing else till reset. Story then was it
enabled some level of factory testing of the die for
the is it even alive test.
Allison
>
>Subject: Re: 6800 opcode $02
> From: "J.C. Wren" <jcwren at jcwren.com>
> Date: Tue, 30 Aug 2005 21:45:00 -0400
> To: General Discussion: On-Topic and Off-Topic Posts <cctalk at classiccmp.org>
>
> I'd suggest finding a VHDL or Verilog implementation, and see if
>that provides any insight. Also, Google for '6800 undocumented opcodes'
>(no quotes). There are a number of hits. Most seem to indicate that
>the undocumented opcode (no value given) causes the processor to go into
>a mode where there are no instruction fetchs, but the address bus runs
>incrementing bus cycles.
>
> --jc
>
>Scott Stevens wrote:
>
>>On Mon, 29 Aug 2005 17:53:59 +0100 (BST)
>>ard at p850ug1.demon.co.uk (Tony Duell) wrote:
>>
>>
>>
>>>Does anyone know what Opcode $02 is on a Motorola 6800 processor. It's
>>>
>>>not defined in the data sheet, but I have a device which forces that
>>>instruction onto the data bus in one of the test modes.
>>>
>>>Is it, by any chance, the infamous HCF instruction?
>>>
>>>-tony
>>>
>>>
>>>
>>Hmm, all the other $0x opcodes on the table are inherent instructions
>>that mess with the condition code register. Looking at the order of the
>>bits in the instructions, I don't see an order that corresponds with
>>good old HINZVC (we were required to memorize this, the order of the
>>bits in the condition code register, in tech school)
>>
>>0a clears overflow (V)
>>0b sets overflow (V)
>>0c clears carry (C)
>>0d sets carry (C)
>>0e clears interrupt mask (I)
>>0f sets interrupt mask (I)
>>
>>The lower instructions defined are
>>06 Accumulator A to CCR
>>07 CCR to Accumulator A
>>
>>
>>Is there a bit-level 'Opcode Breakdown' reference for the 6800
>>processor, that defines bit field and gives clues to how the opcodes are
>>translated in hardware, like there is (it's an elaborate table and I
>>even have a machine language Textbook that drags you through it all on
>>an early chapter) for the 8086 processor?
>>
>>The good old 6800. 'Freescale' : bah!
>>
>>
>>
Hey I was just curious, because I don't see DECmail-11 listed on
Mentec's or HP's website, does that mean that they don't care about
DECmail-11 anymore? If so, does anyone know where I can get a copy?
Julian
Hello folks,
who has experience with the Emulex SC02/C controller?
I tried the hardware format sequence - but it didn't work as expected.
Perhaps my controller has a problem. Perhaps there is something set up
wrong.
And hardware formatting my disk packs is the way I hope to get these
packs usable.
In my documentation to the controller there's mentioned a diagnostic
software - which I don't have. Does anybody have that?
Best wishes,
Philipp :-)
Hi,
does anyone have a manual for one of these? It says graphics terminal on it,
is it a vector terminal like the Tektronix units, or some other device?
Thanks
Jim.
Please see our website the " Vintage Communication Pages" at WWW.G1JBG.CO.UK
