on 11/26/05 2:33, cctalk-request at classiccmp.org at
cctalk-request at classiccmp.org wrote:
I am located in Cary, IL. this is about halfway between
Chicago and Rockford in northeastern Illinois. I will
send items any way desired (assuming USPS Media rate
will be cheapest). Available for shipping costs, or
free if someone picks up anything.
thank you for taking the time to write.
Bradley Slavik
> Brad,
>
> Where are you located?
>
> Lyle
> --
> Lyle Bickley
> Bickley Consulting West Inc.
> Mountain View, CA 94040
>
> \"Black holes are where God is dividing by zero\"
>
>Subject: Pinout for SED9421
> From: lee davison <leeedavison at yahoo.co.uk>
> Date: Sat, 26 Nov 2005 02:50:31 +0000 (GMT)
> To: cctalk <cctalk at classiccmp.org>
>
>> Figures.. However they loose a full sector for every four
>> which is pretty bad considering sync and other overhead that
>> floppies incur.
>
>It's not that clever. One 2K block of data per track, no sectors,
>no sync, just the 125Kb/s async bitstream. Wait for the index
>pulse and read/write the whole track. At the time it was a lot
>cheaper than any other disk controller.
>
>Lee.
They trade being efficient for a lot. Across 35 tracks (sa400) thats
about 18k. NS* hard sector was 10x256 (2560bytes) track, and a
sync chip (one sector per track) will give that much maybe more
as well.
I think what they did was very clever and dirt cheap and the hidden feature
of async is the extra two bit times allows a bit more time to read/write the
port 80uS vs 64uS typical.
Wacky, but soon as you said OSI.. ;) they were a creative lot.
Allison
> Figures.. However they loose a full sector for every four
> which is pretty bad considering sync and other overhead that
> floppies incur.
It's not that clever. One 2K block of data per track, no sectors,
no sync, just the 125Kb/s async bitstream. Wait for the index
pulse and read/write the whole track. At the time it was a lot
cheaper than any other disk controller.
Lee.
..
___________________________________________________________
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>
>Subject: Re: Pinout for SED9421
> From: "Chuck Guzis" <cclist at sydex.com>
> Date: Fri, 25 Nov 2005 17:42:33 -0800
> To: cctalk at classiccmp.org
>
>On 11/26/2005 at 12:48 AM ard at p850ug1.demon.co.uk wrote:
>
>>Is the difference in inertia between the band and the leadscrew really
>>that significant? I always thought the taught band was indroduced for
>>cheapness...
>
>Micropolis drives were 30 ms. track-to-track. I believe they used a 4-step
>per track scheme. The last Micropolis 5.25" drive (with buffered seek) I
>have has a closed-loop tach belt-drive spindle motor. I've never verified
>it, but I suspect that with longer seeks, the stepping rate is sped up
>considerably. I recall fooling with the step rate on a paper-feed motor on
>a printer and discovering that once you've established direction, you can
>crank the stepping rate pretty far up. Try it before things really get
>moving and you're likely to find yourself stepping backwards.
>
>But you have a point about the speed. I've got some Siemens 8" drives that
>use leadscrew positioning and they do just fine at 8 msec. track-to-track.
The real problem is you can only step a stepper so fast. Older and smaller
steppers tended to go async at relatively low speeds.
A band position needed one maybe two steps per track some of the leadscrews
were anywhere from 2(very fast ones) to 8. At some point you hit the wall
for speed. Between resonance and other oddities steppers are hard to use
for fast and precise at the same time.
Allison
>
>Subject: Pinout for SED9421
> From: lee davison <leeedavison at yahoo.co.uk>
> Date: Sat, 26 Nov 2005 01:13:45 +0000 (GMT)
> To: cctalk <cctalk at classiccmp.org>
>
>>> 6850 Async UART clocked at 125K bits/s, and a PIO for the control
>>> lines.
>
>>> Lee.
>
>> Sure it wasnt the 6852 SSDA? UARTs generate start and stop bits and
>
>I checked the OSI610 schematic before replying. 8^)=
>
>Lee.
Figures.. However they loose a full sector for every four which is
pretty bad considering sync and other overhead that floppies incur.
I'd used the 6850 in my first tape system back in '75-76 as it was
available and worked well without baud rate clock scaling to do block
replaceable FM format at around 30 kbaud. Problem was the tapes I used
only got 60k of usable storage due to overhead. Going to a sync part
upped that to 80k. Then I found a decent floppy that was affordable.
Allison
>> 6850 Async UART clocked at 125K bits/s, and a PIO for the control
>> lines.
>> Lee.
> Sure it wasnt the 6852 SSDA? UARTs generate start and stop bits and
I checked the OSI610 schematic before replying. 8^)=
Lee.
..
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>
>Subject: Pinout for SED9421
> From: lee davison <leeedavison at yahoo.co.uk>
> Date: Sat, 26 Nov 2005 00:43:13 +0000 (GMT)
> To: cctalk <cctalk at classiccmp.org>
>
>>> Also Ohio Scientific, I think that was with an async UART?
>>> (Don't know for sure, but I do know the best way to get the
>>> correct information is to post incorrect information!)
>
>>> Tim.
>
>> I think the part they used was an USART as in async, bisync,
>> and HDLC/.x25 kinda thing.
>
>> Allison
>
>6850 Async UART clocked at 125K bits/s, and a PIO for the control
>lines.
>
>Lee.
Sure it wasnt the 6852 SSDA? UARTs generate start and stop bits and
even for a 128 byte sector that's 32 lost byte times as overhead.
You could use a UART though but, storage efficientcy is then degraded.
I went that path to do tape (FM encoded) so it's familiar.
All of the designs I'd seen used synchronous serial parts from the old
com2601/2651/2661 family and relatives under different names.
Allison
>> Also Ohio Scientific, I think that was with an async UART?
>> (Don't know for sure, but I do know the best way to get the
>> correct information is to post incorrect information!)
>> Tim.
> I think the part they used was an USART as in async, bisync,
> and HDLC/.x25 kinda thing.
> Allison
6850 Async UART clocked at 125K bits/s, and a PIO for the control
lines.
Lee.
..
___________________________________________________________
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>Subject: Re: Pinout for SED9421
> From: shoppa_classiccmp at trailing-edge.com (Tim Shoppa)
> Date: Fri, 25 Nov 2005 09:31:03 -0500
> To: cctalk at classiccmp.org
>
>> FYI:the average PLL is a bear to build and debug, they required clean
>> power and good board layout with ample groundplanes. The digital ones are
>> very good, simple to layout and shift rates with only a mux.
>>
>>
>> Allison
>
>Don't neglect: PLL's require analog components of rather tight tolerances
>to give consistent behavior from time-to-time and unit-to-unit.
That falls in the catagory of a bear to build part.
>The digital data separator (I heard its designer once refer to it as
>a "jerk-locked-loop") has no such tight tolerances and in fact is usually
>driven from a crystal oscillator.
That is a good description. It also depends on the number of bits used
as to how locked it is. Really only makes a difference when the peak shift
is bad due to impropper media or bad write precomp or the drive speed is
really off. Usually fixing the drive speed is easiest. The upside is
predictable performance and repeatability.
>The one-shot-with-critical-RC-constant used in early FM data separators
>is a good example. With a little tweaking it really works pretty well.
>But imagine mass-producing such a beast and training the assembly line
>people to do the tweaking, as well as field service, as well as ...
>(Of course us hackers don't mind!)
I hate analog oneshots unless they are timing uncritical. I worked with
an engineer that did everything with onshots and his stuff was prone to
wandering off or plain quitting.
The all time worst was the 1771 internal data sep. Tandy initally did that
to save parts. Really bad.
Allison
