I recently acquired a California Computer Systems model 2422 Floppy Disk
Controller Rev B. (S-100) in what appears to be good condition but
missing a 2716 EPROM presumably containing the onboard BIOS.
Does anyone have this card and the capability of providing me with a
copy of the PROM or at least a dump of it? I'd also love to get my
hands on the docs, if available.
Thank you,
Erik
Hi,
While hauling some VAX and StorageWorks stuff yesterday, I bumped
into a Philips PTS6000 machine (actually, two.. a larger one, and
a smaller one), some HP stuff (looks like HP Big Iron) and the
cabinet of a DECarray system.
Anyone interested? Pics available.
--fred
I was wondering if there ever was a PC PS2 type mouse addon card for old 386
or previous AT type computers?
I know there were bus mice, but thats not the same.
The reason I am asking is because I have a PS2 KVM switch and want to get my
386/DX40 computer connected to it (it doesnt have a ps2 header).
On Feb 9, 10:55, Eric Smith wrote:
> > Are you sure? My understanding is that PLP and PLA increment the
stack
> > pointer *before* fetching the byte off the stack.
> [...]
> > Maybe you're thinking of PHP and PHA ([SP]:=A; SP:=SP+1), which
take one
> > cycle less than PLP/PLA?
>
> You're right, I was confused.
Phew! I was beginning to wonder if the 6502 is more bizarre than I
already knew :-) You missed the mistake though -- I should have
written SP:=SP-1 (no it wasn't a test, I only just noticed).
--
Pete Peter Turnbull
Network Manager
University of York
On Feb 8, 19:02, Eric Smith wrote:
> Well, I haven't counted them, but pretty much all instructions that
> use the ALU do that. This includes ADC, SBC, ORA, AND, EOR, BIT,
> and (when the accumulator is the destination) LSL, ASR, ROR, and ROL.
> And the PLP and PLA instructions, which increment the stack pointer
> using the ALU during the next fetch.
Are you sure? My understanding is that PLP and PLA increment the stack
pointer *before* fetching the byte off the stack. The 6502 stack
pointer always points to the next free location on the stack. It's
possible that it does something like:
fetch instruction
decode, and set up ALU to generate SP+1
fetch [SP+1]
add 1 to SP while fetching next instruction
Maybe you're thinking of PHP and PHA ([SP]:=A; SP:=SP+1), which take
one cycle less than PLP/PLA?
--
Pete Peter Turnbull
Network Manager
University of York
PS2 works off the keyboard controller, I was hoping somebody might have made
a specialty board with keyboard controller allowing older machines to use
ps2 hardware
----- Original Message -----
From: +ACI-John Allain+ACI- +ADw-allain+AEA-panix.com+AD4-
To: +ADw-cctalk+AEA-classiccmp.org+AD4-
Sent: Sunday, February 09, 2003 12:37 PM
Subject: Re: PS2 Mouse
+AD4- +AD4- I could use a USB +AD0APg- PS/2 mouse adapter, so far I have not
+AD4- +AD4- found any such animal. I've found plenty that go the other way.
+AD4-
+AD4- Think this is one. It isn't a passthru.
+AD4- http://www.cyberguys.com/cgi-bin/sgin0101.exe?T1+AD0-131+-0870
+AD4-
+AD4-
+AD4- On the subject...
+AD4- I see a lot of PS/2-female to RS232/D9-male adaptors.
+AD4- I assume that these are for signal sensing mice,
+AD4- since these adaptors Are passthru, and I get the impression
+AD4- from this list that PS/2 signals aren't RS232.
+AD4-
+AD4- John A.
Hi,
I have a large binder containing a DEC PDP11 RSX-11M System Generation and
Management Guide, version 3.2, June 1979. Also included is a RSX-11M/M-Plus
MCR Operation Manual and two bound mini references. All are in excellent
shape. Best offer + shipping.
Thanks Norm
>I'd hate to
>hose the PalmOS flash - dunno if there's a way to get it back without
>building your own external re-Flasher (in the case of the IIIs and older
>that *have* removable SIMMs).
I think they may have an ability to recover built in.
I know when I upgraded the OS on my wife's IIIx, I had a problem with the
upgrade, and the flash didn't complete. The Palm wouldn't boot and I
thought I was hosed. But a check in the directions offered a recover
method. There is a sequence of button presses you can do that drops the
Palm into "debugger" mode, and from there, the upgrade utility could
restart the flash process and write the OS again.
Of course, you would need a copy of the Flash ROM/OS and a utility to
write it. I know you can dump your current ROM to file with the tools in
the Palm Emulator available from Palm... but the only tool I know to
write it back to the Palm is their OS upgrade tool, which means you would
have to shell out for the upgrade (or find someone else that already did
and use the software that they have).
-chris
<http://www.mythtech.net>
I have been searching for info of an old laptop computer i have .
Following details are all i have found:
Attache' Forefront 286
model : LV-286D
power supply : 17Volt ? 2.7Amp ?
Battery : 12Volt 2200mAH NiCAD
3 pin connector - 9.8"x2.1"x1.1"
Has detachable keyboard.
Does any know if manufacturer was taken over by another?
Need details of power supply and battery connector pollarity and or gifs of
same .
Don't know where else to look.
Thanks Paul
On Feb 8, 11:41, Eric Smith wrote:
> Pete wrote:
> > You must be thinking of some different 6502 to the rest of us :-)
As
> > Sellam said, no 6502 opcode takes less than two clock cycles to
> > execute, and most take more (up to 7): the only 2-cycle
instructions are
> > the ones with implied addressing, like RTS, CLI, TAX, ...
>
> Not RTS, that takes a bunch.
Oops, wrong column! Yes, it takes 6.
> There is a little bit of pipelining internally, but it's not really
> obvious. The last ALU operation of an instruction is generally done
> during the same clock cycle as the fetch of the next instruction.
> For instance, when you do an "ADC #35" instruction (add with carry
> immediate), it's a two-cycle instruction, but it really takes three
> cycles to complete -- the third cycle is overlapped with the
following
> instruction's fetch. During the first cycle the opcode is fetched,
> during the second cycle the immediate operand is fetched, and during
the
> third cycle, which is the first cycle of the next instruction, the
actual
> add occurs.
True. Most instructions don't work like that, though.
> > There aren't two CPU cycles per clock cycle. Perhaps you're
thinking of
> > the fact that the 6502 uses a two-phase clock, and does part of the
CPU
> > cycle during phi-1, and part during phi-2?
>
> Perhaps the original poster thought that, but it's just the old
standard
> two-phase NMOS logic. It takes two phases to do just about anything
> internally, so it's not a matter of doing two things sequentially in
> one clock cycle. (A small number of things occur in parallel in some
> cycles, though.)
Yes, *I* know that, but I don't think Jim did :-)
--
Pete Peter Turnbull
Network Manager
University of York