My recollection was that the theoretical speedup of 4x was what one
GATE would do if it lived alone. However once you put all these gates
together (ie, 20K of them), it was the long and short path routing around
that die that ultimately limited the total DEVICE speedup. Further,
DEVICE to DEVICE path lengths on the PCB limited the total system clock
rate and we put a lot of stuff in there to dynamically tune the clock
nets across the board but in the end, the highest reliability occured
clocking at 7nS in liquid and 14nS in air.
We did a lot of speed testing by shmooing the clock and bin'ing the
parts based on how fast they would go at room temp. Ultimately, some
statistics were developed that helped us further "guess" which ones
would make it to at least 7nS in liquid. Some didn't though and you
didn't find that out until they were on the board and the board was in
the liquid. We got pretty good at not doing that near the end though.
Accurate speed testing and looking at ring oscillator rates at room temp
helped predict the performance in liquid pretty well as I remember it.
Each device was pretty much capable of testing itself in this process.
Using the BIST (boundary scan test logic) we could shift in an initial
pattern, run the device at various clock rates for exact numbers of clock
cycles and then shift off the results to compare against simulation.
We'd do initial testing at 4 million clocks and then a more production
like test at 4 billion clocks. The difference between the two was
the cost (in waiting for the run) of simulating that many cycles on
a CY205. Running the actual part that many cycles was a no brainer.
We used various off the shelf GPIB pulse generators as the clock source
in a bench tester and we had a ALSI20K array (AAZB to be specific) that
handled this BIST interface on the ETA10 PCB and ultimately we put that
array on a PC-AT plug-in card and it became part of our bench top tester.
Was fun stuff to be sure.
I am not aware of any other cryogenically cooled machines in that
time frame. We were always competing against Cray doing liquid cooled
(Fluorinert) systems and other air cooled Japanese designs at the time.
Chris
On Friday (02/14/2014 at 03:42AM +0000), Alexey Toptygin wrote:
I've been reading about the ETA-10 systems, and I have some
questions that I hope the folks can clear up for me:
The wikipedia page:
http://en.wikipedia.org/wiki/ETA10
claims that the designers were expecting a theoretical 4x speedup
from cooling the CMOS from room temperature (~300K) to ~90K, but
only attained a 2x speedup in practice. None of the sources I can
find mention the expected 4x speedup; many mention that a 2x speedup
was obtained; some also mention that the originally advertised cycle
time was 5ns, and that only 7ns was ever achieved.
Is there any basis for the wikipedia claim that a 4x speedup was
expected? If so, what's the physics behind that expectation?
Why would the theoretical performance not be attainable in practice?
The most interesting references I've found so far are:
http://www.museumwaalsdorp.nl/computer/en/eta10p.html
http://www.ed-thelen.org/comp-hist/super-users-view.html
http://yarchive.net/comp/eta_peglar.html
There's also an article at ieee that I don't have access to:
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=30952
One last question: are folks aware of any other high performance
computing systems that shipped (to customers, plural :-) to with
cryogenic cooling?
Alexey
--
Chris Elmquist