At last! After far too many OS-advocacy messages, we have something related to classic computers. Can we have more of these please? I don't have a full service manual, but I do have scheamtics (in front of me). The stepper control circuit is pretty simple, and I would have thought you could sort it out from schematics alone. A disk drive exerciser [1] is very useful for doing tests on this circuit, but you can probably use your host system with suitable programming. What uou need to be able to do is send step pulses with the direction line in both states. [1] Those who know me will realise this is just about the only sort of exerciser I am ever likely to use :-) There are 2 inputs to the stepper corciot from the disk controller, the step pulse and the direction signal. These are buffered by U2Ee ('14) and U3Dc ('04) respectively). The inverted step pulse (output of U2Ee) is on TP12. The stepper motor control counter is built from the 2 sections of U4C ('74) along with hte XOR gates U5Da and U5Db ('86), which control the count sequence depending on the state of the direction line. Now look at the clock input to this counter. It comes from U4Ba ('20), which gates the step pulse (TP12, as above). The counter can only count if the drive is selected and it's not writing. And if one other signal (output of U4Fc, '38) is high. This gate prevents the drive stepping outwards if the track 0 signal is asserted. And I wonder if that's where your problem is. If track 0 is stuck asserted, then you won't be able to step outwards. The track 0 signal is based round U4Bb ('20), whioch combines the output of the track 0 sensor circuit (in a minute...) with the outptus of the counter flip-flops (thus making the exact trigger postiion of the sensor less critical). The output of U4Bb is inverted by U3Da, and fed both to the interface connector (via U1Fd, '38) and into the step clock gating circuit. Start by looking at the output of U4Bb (also on TP8). If that's low, then the drive thinks it's at track 0, and won't allow outward stepping. The track 0 zensor it a microswitch (!) connected to P11. It's debounced by U4Fd and U4Fa ('38), cross-coupled to make an SR flip-flop. Now, I've had problems with the microswitches in these drives (not suprising given their age). I had to replace one in my HP9836A. It worked _some of the time_. Other times the track 0 signal would latch on (i.e. the switch made on one contact, flipped the SR one way, but didn't make on the other contact when the heads moved off cylinder 0, so the SR was never flopped back). You can still get a suitable microswitch. It's a normal V3 package but with a low (15g?) operating force. I found a suitable one from RS components (IIRC, may have been Farnell). Fitting it is not too hard, but you should do a track 0 alignment afterwards. I found that if you mark the position of the bracket on the chassis before removing it, and if you mark the position of the swtich on the bracket, and put everything back in the same place, it'll be near enough to work. I have a 'Microtest' alignment system so doing it properly was easy. Let me know how you get on, I'l suggest further things to check/try. -tony