<timing failure? Have you examined the nRAS nWE and nCAS signals to the DRA <with your 'scope? Where does this DMA live? Is this an i8257 on the <controller? I'll bet not. Ramtiming is not half the problem on s100 as the general design of the board. Some of the Dram cards use the inactive bus state of the 8080/z80 to do hidden refresh, some do it after every nth read or 16us which ever come first, a few try to hide it as part of a read or write. Most all do not have any arbitration to resolve a DMA request. generally DMA and S100 before 1980or later was at best an iffy situation and only likely to work if a whole cardset of a given vendor was used. The reason for the latter was the interpretation of s100 was not stable till 79ish or later (actually even after the 696 spec was published). Anyhow, do to timing vaiations, arbitration problems and many poor DRAM designs most people prefered static and avoided DMA. The only two systems I know of that DMA is Compupro and Ithica Intersystems. There are a few slaves (JADE, IMSAI (8080/372based) but, most used the main cpu in a tight loop doing PIO. Oh, yes, that reminds me. Some of the DRAM cards really hated the Floppy cards that would do a wait/data stall by pulling PWAIT to keep the CPU in sync without testing a port bit (northstar, MDC, others). Allison