2 Oct
2007
2 Oct
'07
7:10 a.m.
Subject: TI 990 architecture / was Re: TI-99/4A Floppies
From: Brent Hilpert <hilpert at cs.ubc.ca>
Date: Tue, 02 Oct 2007 00:35:01 -0700
To: General at priv-edtnaa06.telusplanet.net,
"Discussion at priv-edtnaa06.telusplanet.net":On-Topic and Off-Topic Posts
<cctalk at classiccmp.org>
Chuck Guzis wrote:
Actually 1980 was mid to late in the life of the TI9900 chip. The first
one I worked with was on a Technico Superstarter System, TI9900, 2k ram,
1k prom (monitor ans line by line asm) and a 2708 eprom programmer on
one board. I still have it. I purchased it at PCC '78 in in memory
serves Philly. Fir the amount of resource on the board it was pretty
capable for systems of that day.
On 2 Oct 2007 at 2:16, Liam Proven wrote:
I can't state so categorically but my understanding is that they were very
much the same.
Going back to a conversation of a few weeks ago, when we were
developing/running Verex/Thoth at UBC ca 1980 it was on a 990/10. The next
major step in the project was to develop a distributed kernel for multiple
processors. To this end, 3 bare single board computers based on the 9900 chip
were ordered and received from TI. Something makes me think they were called
"990/5"s. I remember making up a front panel for the 3 of them with reset
buttons and a few status LEDs to go in the rack with the /10. The idea, of
course, was to use the 9900s because we already had the compilers,etc.
generating code for the 990/10. They were pretty much the first ever 16-bit home
micro, but it was a
crippled 16-bit chip - as detailed in another message in this thread.
They did have good keyboards, were solidly built and I believe the
graphics chip was, for its time, decent and capable.
Tossing all of the other chips and CROMs and other stuff out, how
compatible was the TMS9900 with the TI 990 mini? The same or
considerablly different? (Cheriton left before we actually got into using them
at the software level
and the distributed kernel would become the VKernel at Stanford on other hardware).
Also, the description of the 9900 in Osborne's "An Introduction to
Microcomputers, Vol II" ('76) fits well with my recollections of the 990/10.
To my knowledge the 9900 chip was not crippled; rather (going from what others
have described) the design and implementation of the 99/4 home computer failed
to make effective use of it. I didn't follow micros too much in the early 80s
but I remember wondering at the time why the 99/4 was doing so poorly when it
had that great processor in it.
There are really three 99/4 home computers, original with chiclet keys, the
second and most common with a really nice keyboard and the whie version that
is really the same thing with a few board level cost reductions.
The 9900 chips is not crippled, for 1976 three voltage NMOS its about as fast
as the technology of the time could go. The TI99/4 did however do a nasty to
it. One is they muxed the bus down to 8bits wide and that does slow the system
some. There were 128 words of ram (6810s) that if you execute there the speed
is noticeable. The other is the GROM (sort of an interpreted language with a
register point to next instruction) is a bottleneck as well. There was a
later 9980 and the 9985 which were a 8bit bus interface and were somewhat
crippled but I'd never seen one in a TI99/4A.
I quite liked the 990 architecture with the workspace
pointer. Yes, there was
the overhead of accessing registers in memory, but there were also savings.
The workspace pointer essentially became the stack/frame pointer. Procedure
calls, interrupts and process switches were quick because there were only 3
machine registers to save (PC,WSP,PSW). Stack variables and parameters were
referenced in instructions as registers, thus saving on instruction
length/memory accesses to retrieve addresses/offsets, etc. For use with
"modern software design", i.e.: stack-oriented high-level languages, I thought
it was a quite effective architecture.
It was a very minicomputer in look and feel and the addressing modes were on
par with PDP11 and other CISC machines.
Allison
2 Oct
2 Oct
12:18 p.m.
On 02/10/2007, Allison <ajp166 at bellatlantic.net> wrote:
The 9900 chips is not crippled, for 1976 three voltage
NMOS its about as fast
as the technology of the time could go. The TI99/4 did however do a nasty to
it. One is they muxed the bus down to 8bits wide and that does slow the system
some. There were 128 words of ram (6810s) that if you execute there the speed
is noticeable. The other is the GROM (sort of an interpreted language with a
register point to next instruction) is a bottleneck as well. There was a
later 9980 and the 9985 which were a 8bit bus interface and were somewhat
crippled but I'd never seen one in a TI99/4A.
That's probably true, but the 99/4a wasn't a 1976 machine. It was
released in 1981 and withdrawn 1983. A bit unfairly for a tweaked 1979
machine (the 99/a), the 99/4a's competition was mainly 1982 machines
like the Commodore 64 and Sinclair Spectrum, which (based on my
possibly erroneous recollection) outperformed the 99/4a significantly.
--
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12:43 p.m.
New subject: TI 990 architecture
> The 9900 chips is not crippled, for 1976 three
voltage NMOS its about as fast
> as the technology of the time could go. The TI99/4 did however do a nasty to
> it. One is they muxed the bus down to 8bits wide and that does slow the system
> some. There were 128 words of ram (6810s) that if you execute there the speed
> is noticeable.
If I remember right, the architecure of the ti chip
it used a pointer to ram as the internal registers. That would really
bog down on byte wide bus. The year sounds right as
I remember BYTE talking about the chip. One of the few times
you had BYTE not looking at 8080/Z80 cpu's.
Ben.
12:57 p.m.
New subject: TI 990 architecture
If I remember right, the architecure of the ti chip
it used a pointer to ram as the internal registers. That would really
bog down on byte wide bus.
But then chips like the 9995 do very well on a 8-bit data bus. IMHO the
bigger problems with the 9900 implementation in the 99/4A were the external
scratch pad (made internal for the 9995) and the presence of GROMs,
requiring their own interpretation step and murderously slow serial access.
Compare this to a system like the Tomy Tutor, which has a 9995 on an 8-bit
bus too, but is significantly faster than the 99/4A despite being clocked
slightly slower (10.7MHz oscillator instead of the 99/4A's 12MHz one).
--
------------------------------------ personal: http://www.cameronkaiser.com/ --
Cameron Kaiser * Floodgap Systems * www.floodgap.com * ckaiser at floodgap.com
-- Everything you think you know is wrong. -- Jack Chalker --------------------
1:17 p.m.
New subject: TI 990 architecture
woodelf wrote:
Yes thats true. Fortunately the address bus was not munged up but all
the registers and the pointers they form are 16bit so a split bus slowed
things some due to the limitations of ram speed. What was done was at the
point in the processor read, write or RMW cycle they would insert a wait
and then mux/demux the bus depending on direction. The overall cost was
around two wait states due to ram speed rather than CPU speed. Since the
bus splitting was done outside the CPU it was less costly then the 9080
flavor.
Actually the 9900 was a fine chip and there were faster versions never
really got marketed. It was the first real 16bitter.
Allison
> The 9900 chips is not crippled, for 1976
three voltage NMOS its about
> as fast
> as the technology of the time could go. The TI99/4 did however do a
> nasty to
> it. One is they muxed the bus down to 8bits wide and that does slow
> the system
> some. There were 128 words of ram (6810s) that if you execute there
> the speed
> is noticeable.
If I remember right, the architecure of the ti chip
it used a pointer to ram as the internal registers. That would really
bog down on byte wide bus. The year sounds right as
I remember BYTE talking about the chip. One of the few times
you had BYTE not looking at 8080/Z80 cpu's.
Ben. 
3 Oct
3 Oct
10:36 a.m.
New subject: TI 990 architecture
While a workspace point defining the location of a set of "registers"
in main memory sounds like a good idea, is it? While one avoids the
need for 16 words of on-chip register RAM, it comes at a cost of
making an external memory access (not to mention an address
calculation) each time a register is addressed (most of the
instructions do this, so the cost in cycles is very high).
It seems to me to be far better to employ the S/360 method of using
STM/LM-type instructions to change the context. The multiple
register load and store instructions are present on many other CPUs
since then, but it seems that S/360 was the first to make use of
this.
While the in-memory "registers" could certainly be cached by the CPU
(watch out for "dual" reference issues!), that seems to be less
flexible than an architecture that allows any number of registers to
be stored or loaded explicitly as part of a context switch.
Thoughts?
Cheers,
Chuck
12:10 p.m.
New subject: TI 990 architecture
Chuck Guzis wrote:
While a workspace point defining the location of a set of "registers"
in main memory sounds like a good idea, is it? While one avoids the
need for 16 words of on-chip register RAM, it comes at a cost of
making an external memory access (not to mention an address
calculation) each time a register is addressed (most of the
instructions do this, so the cost in cycles is very high).
It seems to me to be far better to employ the S/360 method of using
STM/LM-type instructions to change the context. The multiple
register load and store instructions are present on many other CPUs
since then, but it seems that S/360 was the first to make use of
this.
While the in-memory "registers" could certainly be cached by the CPU
(watch out for "dual" reference issues!), that seems to be less
flexible than an architecture that allows any number of registers to
be stored or loaded explicitly as part of a context switch.
Thoughts?
My 'feeling' was that for general purpose computing and modern software
developed in stack-oriented languages, with a lot of function calls/system
calls/context switches/argument passing - where the focus of data activity is
around the stack - relative to the amount of 'basic' calculation, the benefits
of machine registers becomes less due to the amount of save/restore/other
stack work that has to be done one way or the other.
(An informed judgement needs piles of program execution profiling data at
hand, but then I do believe the issue has been studied to death.)
I'm not very familiar with modern RISC processors at the machine level, but I
thought that was the direction general purpose RISC processors had gone with
register windows & c. Nowadays high speed cache reduces the margin of benefit
of machine registers and one can throw a lot of straight combinatorial logic
at address calculation to minimise the amount of time needed for such.
For things like DSPs where one is doing a lot of the same calculation on a
(perhaps narrower) stream of data in time sequence I can see the benefit of
sticking more towards machine registers (or vector machine registers).
2 Oct
2 Oct
1:24 p.m.
On 2 Oct 2007 at 20:18, Liam Proven wrote:
That's probably true, but the 99/4a wasn't a
1976 machine. It was
released in 1981 and withdrawn 1983.
No, but I think the point was that the TMS9900 itself was a 1976-
release chip. But then, so was the GI CP1610 and that saw plenty of
use in Intellivision consoles, even though it was pretty much the
same as the also-16-bit GI 1600, released in 1975.
Cheers,
Chuck
3 Oct
3 Oct
9:48 a.m.
On Oct 2, 2007, at 3:47 PM, Martin Scott Goldberg wrote:
What are the differences between them, does anyone know offhand?
-Dave
--
Dave McGuire
Port Charlotte, FL
Farewell Ophelia, 9/22/1991 - 7/25/2007
There are
really three 99/4 home computers, original with chiclet
keys, the
second and most common with a really nice keyboard and the whie
version that
is really the same thing with a few board level cost reductions.
Actually, there's one TI-99/4 and two TI-99/4a models. 
10:13 a.m.
Actually 1980 was mid to late in the life of the TI9900 chip. The first
one I worked with was on a Technico Superstarter System, TI9900, 2k ram,
1k prom (monitor ans line by line asm) and a 2708 eprom programmer on
one board. I still have it. I purchased it at PCC '78 in in memory
serves Philly. Fir the amount of resource on the board it was pretty
capable for systems of that day.
That sure brings back memories. I also had a Technico SuperStarter (Two bytes
are better than one!) Eventually made a wire wrapped 32 KByte RAM card (using
TMS4060 non muxed 4K DRAMS), a 256x256 graphic display, A wire wrapped floppy
controller (8 inch with 16 KByte DRAM track buffer). The floppy was a
revelation after waiting for the papertape version of EAL (Editor Assembler
Linker?) to load.
> (Cheriton left before we actually got into using them at the software level
> and the distributed kernel would become the VKernel at Stanford on other hardware).
>
> Also, the description of the 9900 in Osborne's "An Introduction to
> Microcomputers, Vol II" ('76) fits well with my recollections of the 990/10.
I think I chose the 9900 based on the Osborne book, it had the shortest
benchmark program...
Interestingly TI's MSP430 has an instruction set reminiscent of the 9900
Peter Wallace
11:17 a.m.
On 3 Oct 2007 at 10:13, Peter C. Wallace wrote:
I think I chose the 9900 based on the Osborne book, it
had the shortest
benchmark program...
Those benchmarks weren't very comparable! Some had artificial
restrictions placed on them because a "move any number of bytes
anywhere" sample of code would likely take more than a single page of
print. And for many of them, the *size* of the benchmark code wasn't
taken into consideration.
For example, the Z80 benchmark is really shorter than that of the
TMS9900; the 9900 benchmark makes the assumption that the workspace
has been "preloaded" with the operands and that a BLWP was used to
change context--and that words, not bytes, are to be moved. If the
registers used are explicitly loaded and stored, the TMS9900
benchmark would have been much longer.
This overly-simple benchmark with varying assumptions is one of the
biggest weaknesses of Volume II of the Osborne books. Perhaps a
better benchmark might have been searching a character string for a
matching substring.
But even with its weaknesses, the "Introduction to Microcomputers"
set was a valuable resource when there was little software and no MPU
was yet dominant.
Cheers,
Chuck
11:46 a.m.
On Wed, 3 Oct 2007, Chuck Guzis wrote:
Date: Wed, 03 Oct 2007 11:17:06 -0700
From: Chuck Guzis <cclist at sydex.com>
Reply-To: "General Discussion: On-Topic and Off-Topic Posts"
<cctalk at classiccmp.org>
To: "General Discussion: On-Topic and Off-Topic Posts" <cctalk at
classiccmp.org>
Subject: Re: TI 990 architecture / was Re: TI-99/4A Floppies
On 3 Oct 2007 at 10:13, Peter C. Wallace wrote:
It was mainly the source code size of the assembly language and the
minicomputer elegance that I liked (since at that time assembler was all I
knew), In comparison the Z80 instruction set is anything but minicomputer like
or elegant, just a bag on the side of a bag on the side of an 8008.
The registers-in-memory architecture might be suitable for a FPGA CPU where
BlockRAM (as system memory) is almost as fast as registers. Why not have
registers in memory instead of simulatiing it badly (and expensively power
wise) via caching, that is, why move data if you dont have to?
Peter Wallace
I think I chose the 9900 based on the Osborne
book, it had the shortest
benchmark program...
Those benchmarks weren't very comparable! Some had artificial
restrictions placed on them because a "move any number of bytes
anywhere" sample of code would likely take more than a single page of
print. And for many of them, the *size* of the benchmark code wasn't
taken into consideration.
For example, the Z80 benchmark is really shorter than that of the
TMS9900; the 9900 benchmark makes the assumption that the workspace
has been "preloaded" with the operands and that a BLWP was used to
change context--and that words, not bytes, are to be moved. If the
registers used are explicitly loaded and stored, the TMS9900
benchmark would have been much longer.
This overly-simple benchmark with varying assumptions is one of the
biggest weaknesses of Volume II of the Osborne books. Perhaps a
better benchmark might have been searching a character string for a
matching substring.
But even with its weaknesses, the "Introduction to Microcomputers"
set was a valuable resource when there was little software and no MPU
was yet dominant.
Cheers,
Chuck
12:04 p.m.
Peter C. Wallace wrote:
The registers-in-memory architecture might be suitable
for a FPGA CPU
where BlockRAM (as system memory) is almost as fast as registers. Why
not have registers in memory instead of simulatiing it badly (and
expensively power wise) via caching, that is, why move data if you dont
have to?
Simple registers are expensive. Look at the PDP-5. This is the 1960's
when most architectures where developed. Even the PDP-10 I think
was designed to use core memory as registers unless you want the
optional module for F/F registers.
Ben.
12:56 p.m.
Chuck Guzis wrote:
On 3 Oct 2007 at 10:13, Peter C. Wallace wrote:
> I think I chose the 9900 based on the Osborne book, it had the shortest
> benchmark program...
This overly-simple benchmark with varying assumptions
is one of the
biggest weaknesses of Volume II of the Osborne books. Perhaps a
But even with its weaknesses, the "Introduction to Microcomputers"
set was a valuable resource when there was little software and no MPU
was yet dominant.
I love that book, for it's overview of lesser known microprocs and being a
period snapshot of the state-of-the-art. I still find it a useful
technical reference for a lot of chips for which data is hard to come by.
2:58 p.m.
On Wed, 3 Oct 2007, Dave McGuire wrote:
Date: Wed, 3 Oct 2007 17:00:14 -0400
From: Dave McGuire <mcguire at neurotica.com>
Reply-To: "General Discussion: On-Topic and Off-Topic Posts"
<cctalk at classiccmp.org>
To: "General Discussion: On-Topic Posts Only" <cctech at classiccmp.org>
Subject: Re: TI 990 architecture / was Re: TI-99/4A Floppies
On Oct 3, 2007, at 1:13 PM, Peter C. Wallace wrote:
Sure but more TMS9900 like... (plus they got the source and destination
Register addresses on nibble boundaries so the HEX opcode are fairly
readable...)
Peter Wallace
Interestingly TI's MSP430 has an instruction
set reminiscent of the 9900
Rrrr? The MSP430 is *VERY* PDP-11 like.
-Dave
6290
days inactive
6291
days old
16 comments
9 participants
participants (9)
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ajp166＠bellatlantic.net -
bfranchuk＠jetnet.ab.ca -
cclist＠sydex.com -
hilpert＠cs.ubc.ca -
lproven＠gmail.com -
mcguire＠neurotica.com -
pcw＠mesanet.com -
spectre＠floodgap.com -
wgungfu＠csd.uwm.edu