25 Nov
2005
25 Nov
'05
12:49 p.m.
Subject: Re: Pinout for SED9421
From: "Chuck Guzis" <cclist at sydex.com>
Date: Fri, 25 Nov 2005 09:24:30 -0800
To: cctalk at classiccmp.org
On 11/25/2005 at 9:31 AM shoppa_classiccmp at trailing-edge.com wrote:
Simple, the non-digital circuits were available and the chips like 9229/9216
were later. There were really three varients, for plain FM oneshots either
analog or digital did the job well enough. When DD (MFM) started to appear
along with then current drives That didn't work well enough (peak shift)
and PLLs became the solution then around 1981 people started to figure out
how to apply write precomp and digital data seps that were either counter
based or DPLL.
to do the tweaking, as well as field service, as
well as ...
(Of course us hackers don't mind!)
I've got a system here with a rather elaborate analog data separator PLL
(built around a CA3130 op amp). Part of the manufacturing process involves
a calibration diskette, trimpot and scope. It's pretty robust once it's
been set up, but component aging is probably a significant factor in
long-term performance.
It seems hardly any more robust than a plain old digital (9216-type) data
separator. Which makes me wonder why anyone would bother implementing the
data separator in Figure 13 of the 179x app notes (3 trimpots). Out of the stats on performance that Allison cited, how
many of those
errors could be recovered with a simple retry?
Most were soft. Once they started to become hard the media was showing
distress.
When I learned that Jameco was running low on
9216's, I bought their entire
stock, which amounts to about a 2 ft. tube of 8 pin DIPS. So if you're
looking for one, you know who's got 'em. :)
Either that a Dflop(74LS74), hex D-latch(74LS174) and 32x4 prom(74LS288).
Allison
4:08 p.m.
On Fri, 25 Nov 2005, woodelf wrote:
Peter Wallace
Allison wrote:
Heathkit did with their H89 hard sectored floppy controller....
Either that a Dflop(74LS74), hex D-latch(74LS174)
and 32x4 prom(74LS288).
Just for the heck of it, got a schematic and a prom listing?
Did anybody ever use a serial chip and a data separater
rather than a floppy disk controler? 
4:56 p.m.
"Peter C. Wallace" <pcw at mesanet.com> wrote:
On Fri, 25 Nov 2005, woodelf wrote:
Peter Wallace
Also Ohio Scientific, I think that was with an async UART? (Don't
know for sure, but I do know the best way to get the correct information
is to post incorrect information!)
Tim.
Allison wrote:
Heathkit did with their H89 hard sectored floppy controller....
Either that a Dflop(74LS74), hex D-latch(74LS174)
and 32x4 prom(74LS288).
Just for the heck of it, got a schematic and a prom listing?
Did anybody ever use a serial chip and a data separater
rather than a floppy disk controler? 
4:25 p.m.
On 11/25/2005 at 1:51 PM woodelf wrote:
Just for the heck of it, got a schematic and a prom
listing?
Did anybody ever use a serial chip and a data separater
rather than a floppy disk controler?
I've done it on lashups to read very oddball floppies. A 2651 in sync mode
will go to something like 600KHz or 1MHz data rate.
Cheers,
Chuck
7:08 p.m.
In message <4387794F.1020008 at jetnet.ab.ca>
woodelf <bfranchuk at jetnet.ab.ca> wrote:
Allison wrote:
Actually, I wouldn't mind taking a look at the appnote with the data
separator in it. Sounds like something that might be worth reading...
I've just spent two days reverse-engineering the Atari Digital Vector
Generator down to state machine level. Thank %DEITY for schematics!
Only thing I am trying to work out is why the hell the state machine jumps to
state 9 on startup, which is a DMALD microinstruction. Basically, when it
starts up, it pulls an address off the stack and jumps to it. Unless I'm
wrong, that means it jumps to a random address on startup. That is, unless
the LS670 Register File Memory used for the stack is guaranteed to power up
with all registers loaded with 0000(bin), but IMO that's a dangerous
assumption to make without testing.
Just a shame LS670s are pretty much unobtainium these days, otherwise I would
have tested it out...
Thanks.
--
Phil. | Acorn RiscPC600 SA220 64MB+6GB 100baseT
philpem at philpem.me.uk | Athlon64 3200+ A8VDeluxe R2 512MB+100GB
http://www.philpem.me.uk/ | Panasonic CF-25 Mk.2 Toughbook
The Klingon dictionary: 90% curses or your money back.
Either that a Dflop(74LS74), hex D-latch(74LS174)
and 32x4 prom(74LS288).
Just for the heck of it, got a schematic and a prom listing?
Did anybody ever use a serial chip and a data separater
rather than a floppy disk controler? 
7:41 p.m.
Philip Pemberton wrote:
In message <4387794F.1020008 at jetnet.ab.ca>
woodelf <bfranchuk at jetnet.ab.ca> wrote:
umm 33 cents each at unicorn electronics. Could the stack be
jamed with 0 on reset?
Ben alias woodelf
Allison wrote:
Actually, I wouldn't mind taking a look at the appnote with the data
separator in it. Sounds like something that might be worth reading...
I've just spent two days reverse-engineering the Atari Digital Vector
Generator down to state machine level. Thank %DEITY for schematics!
Only thing I am trying to work out is why the hell the state machine jumps to
state 9 on startup, which is a DMALD microinstruction. Basically, when it
starts up, it pulls an address off the stack and jumps to it. Unless I'm
wrong, that means it jumps to a random address on startup. That is, unless
the LS670 Register File Memory used for the stack is guaranteed to power up
with all registers loaded with 0000(bin), but IMO that's a dangerous
assumption to make without testing.
Just a shame LS670s are pretty much unobtainium these days, otherwise I would
have tested it out...
Either that a Dflop(74LS74), hex D-latch(74LS174)
and 32x4 prom(74LS288).
Just for the heck of it, got a schematic and a prom listing?
Did anybody ever use a serial chip and a data separater
rather than a floppy disk controler?
Thanks.
7:59 p.m.
I've just spent two days reverse-engineering the
Atari Digital Vector
Generator down to state machine level. Thank %DEITY for schematics!
You're lucky. I normally have to start by producing the schematics (mind
you, for simple stuff, its quicker _for me_ to draw them out than either
to do battle with the manufacturer or to download them and figure out
how to print them...)
Only thing I am trying to work out is why the hell the state machine jumps to
state 9 on startup, which is a DMALD microinstruction. Basically, when it
starts up, it pulls an address off the stack and jumps to it. Unless I'm
Are you sure it does? In particular, are you sure the output of the stack
is not tri-stated and the lines driven by something else?
wrong, that means it jumps to a random address on
startup. That is, unless
the LS670 Register File Memory used for the stack is guaranteed to power up
with all registers loaded with 0000(bin), but IMO that's a dangerous
assumption to make without testing.
Just a shame LS670s are pretty much unobtainium these days, otherwise I would
have tested it out...
I've used the LS170 quite a bit (open-collector, not tri-state outputs),
and I am darn sure the power-up state is not guaranteed to be anything
special.
-tony
26 Nov
26 Nov
3:29 a.m.
In message <m1EfoPa-000IyHC at p850ug1>
ard at p850ug1.demon.co.uk (Tony Duell) wrote:
I've just found another gate that I missed on my first look at the circuit...
The Y_LOW and Y_HI/OPCODE latches are cleared to zero on a reset. That means
the opcode being loaded on startup has a low LSB. That makes the read strobe
for the register file inactive, and the GATE lines for the two address
buffers (H6 and J6) active. They gate Y[11:0] onto the counter inputs and the
counter's LOAD input gets strobed by DMALD. Cute trick...
This thing has logic tricks to rival Woz's IWM (Disk II) floppy controller...
You're lucky. I normally have to start by
producing the schematics (mind
you, for simple stuff, its quicker _for me_ to draw them out than either
to do battle with the manufacturer or to download them and figure out
how to print them...)
If I didn't have the schematics, I'd be SOL - Asteroids and Battlezone arcade
PCBs are getting a bit thin on the ground...
Only thing I
am trying to work out is why the hell the state machine jumps to
state 9 on startup, which is a DMALD microinstruction. Basically, when it
starts up, it pulls an address off the stack and jumps to it. Unless I'm
Are you sure it does? In particular, are you sure the output of the stack
is not tri-stated and the lines driven by something else? I've used the LS170 quite a bit (open-collector,
not tri-state outputs),
and I am darn sure the power-up state is not guaranteed to be anything
special.
I thought as much. "Guaranteed poweron state: None, probably random crap".
Same as pretty much any ordinary SRAM really.
Thanks.
--
Phil. | Acorn RiscPC600 SA220 64MB+6GB 100baseT
philpem at philpem.me.uk | Athlon64 3200+ A8VDeluxe R2 512MB+100GB
http://www.philpem.me.uk/ | Panasonic CF-25 Mk.2 Toughbook
... This is 1 FM. - Quick Mr. Worf close the bloomin' hailing frequencies.
7:23 p.m.
Are you sure
it does? In particular, are you sure the output of the stack
is not tri-stated and the lines driven by something else?
I've just found another gate that I missed on my first look at the circuit...
The Y_LOW and Y_HI/OPCODE latches are cleared to zero on a reset. That means
the opcode being loaded on startup has a low LSB. That makes the read strobe
for the register file inactive, and the GATE lines for the two address
buffers (H6 and J6) active. They gate Y[11:0] onto the counter inputs and the
counter's LOAD input gets strobed by DMALD. Cute trick...
This thing has logic tricks to rival Woz's IWM (Disk II) floppy controller...
Please do not compare an ingenious design with that almighty kludge.
-tony
6790
days inactive
6792
days old
10 comments
7 participants
participants (7)
-
ajp166＠bellatlantic.net -
ard＠p850ug1.demon.co.uk -
bfranchuk＠jetnet.ab.ca -
cclist＠sydex.com -
pcw＠mesanet.com -
philpem＠dsl.pipex.com -
shoppa_classiccmp＠trailing-edge.com