7 Jan
2005
7 Jan
'05
9:43 a.m.
dirt has been known to be found in most places in the world...
doing a wired-or and wired-and depends on reading IC specifications for specific chips. It
is what design engineers do...
-----Original Message-----
From: Tom Jennings <tomj(a)wps.com>
It varies from chip to chip and family to family. Wire OR/etc was
common as dirt.
7 Jan
7 Jan
9:59 a.m.
On Fri, 7 Jan 2005, Steve Thatcher wrote:
dirt has been known to be found in most places in the
world...
doing a wired-or and wired-and depends on reading IC specifications for specific chips.
It is what design engineers do...
Sorry for being so obtuse! Phrase meant: "wire OR/etc was very
common in RTL".
I tried wired-OR once in TTL, didn't like the results :-)
-----Original Message-----
From: Tom Jennings <tomj(a)wps.com>
It varies from chip to chip and family to family. Wire OR/etc was
common as dirt.
4:33 p.m.
On Fri, 7 Jan 2005 12:59:57 -0800 (PST)
Tom Jennings <tomj(a)wps.com> wrote:
On Fri, 7 Jan 2005, Steve Thatcher wrote:
Wired-OR will work fine for open-collector output TTL. It will fail
miserably with totem-pole output parts. A 'battle of the transistors'
will ensue and one output or another will win.
dirt has been known to be found in most places in
the world...
doing a wired-or and wired-and depends on reading IC specifications
for specific chips. It is what design engineers do...
Sorry for being so obtuse! Phrase meant: "wire OR/etc was very
common in RTL".
I tried wired-OR once in TTL, didn't like the results :-)
5:27 p.m.
I tried wired-OR once in TTL, didn't like the
results :-)
Not surprising, since wiring two outputs together generally produces
something much more like wire-AND. :-)
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