8 Feb
2003
8 Feb
'03
9:11 a.m.
On Feb 8, 11:41, Eric Smith wrote:
Oops, wrong column! Yes, it takes 6.
standard
Pete wrote:
> You must be thinking of some different 6502 to the rest of us :-)
As
> Sellam said, no 6502 opcode takes less than two
clock cycles to
> execute, and most take more (up to 7): the only 2-cycle
instructions are
the ones with
implied addressing, like RTS, CLI, TAX, ...
Not RTS, that takes a bunch. There is a little bit of pipelining internally, but
it's not really
obvious. The last ALU operation of an instruction is generally done
during the same clock cycle as the fetch of the next instruction.
For instance, when you do an "ADC #35" instruction (add with carry
immediate), it's a two-cycle instruction, but it really takes three
cycles to complete -- the third cycle is overlapped with the
following
instruction's fetch. During the first cycle the
opcode is fetched,
during the second cycle the immediate operand is fetched, and during
the
third cycle, which is the first cycle of the next
instruction, the
actual
add occurs.
True. Most instructions don't work like that, though.
> There aren't two CPU cycles per clock cycle.
Perhaps you're
thinking of
> the fact that the 6502 uses a two-phase clock,
and does part of the
CPU
cycle during
phi-1, and part during phi-2?
Perhaps the original poster thought that, but it's just the old two-phase NMOS logic. It takes two phases to do just
about anything
internally, so it's not a matter of doing two things sequentially in
one clock cycle. (A small number of things occur in parallel in some
cycles, though.)
Yes, *I* know that, but I don't think Jim did :-)
--
Pete Peter Turnbull
Network Manager
University of York
8 Feb
8 Feb
11:02 a.m.
Pete wrote about my example of the 6502 ADC immediate instruction
being pipelined:
True. Most instructions don't work like that,
though.
Well, I haven't counted them, but pretty much all instructions that
use the ALU do that. This includes ADC, SBC, ORA, AND, EOR, BIT,
and (when the accumulator is the destination) LSL, ASR, ROR, and ROL.
And the PLP and PLA instructions, which increment the stack pointer
using the ALU during the next fetch. Probably others that don't come to
mind at the moment, as well.
The original claim back in 1975 that the 6502 (and fmaily) was pipelined
was probably intended as a comparison to the other microprocessors of
the time, especially the somewhat similar 6800, which took more clock
cycles to do most operations, because it did not have even the small amount
of pipelining of the 6502.
2:37 p.m.
Eric Smith wrote:
The original claim back in 1975 that the 6502 (and
fmaily) was pipelined
was probably intended as a comparison to the other microprocessors of
the time, especially the somewhat similar 6800, which took more clock
cycles to do most operations, because it did not have even the small amount
of pipelining of the 6502.
A hidden gotya is the index registers are 8 bits. No problem
for small dedicated control but somthing that limited high
level languages to Basic and Pascal p-code.
Ben.
5:04 p.m.
ben franchuk wrote:
A hidden gotya is the index registers are 8 bits. No
problem
for small dedicated control but somthing that limited high
level languages to Basic and Pascal p-code.
I'd have to disagree. There were plenty of other HLLs available
for the 6502. The 8-bit index register isn't an issue using
the indirect indexed addressing mode, e.g., "LDA (FOO),Y", in
which any pair of consecutive zero page locations can act as a
16-bit base, with the index register as an offset.
The biggest limitation for HLL support was the 256-byte stack
limit; if you needed more stack you had to roll your own.
It was certainly not as nice as a 6809, but then it predated
the 6809 by several years.
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3 comments
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bfranchuk＠jetnet.ab.ca -
eric＠brouhaha.com -
pete＠dunnington.u-net.com