22 Jul
2018
22 Jul
'18
11:07 a.m.
From: Paul Birkel
Unfortunately there's not much documentation for
the MS11.
??? We're actually pretty well off, there; we have:
- MS11 Maintenance Manual (DEC-11-HMSAA-D-D)
- MS11 MOS Memory Troubleshooting Guide (DEC-11-HMSTS-A-D)
- MS11-B Engineering Drawings
About all we're missing are the MS11-A/C data board engineering drawings.
(The control board is in the MS11-B prints.)
From: Mattis Lind
This could mean that 16 bit data is in the L chips
while the faster
chips are used for a 10 bit cache tag.
Sounds plausible.
And of course those two I/O connectors don't
belong on a cache.
...
Those IO connectors are connected to two double height boards in 26 /27
AB. They are also made by ACT and contain a few TTL chips.
If the board is a cache, how does it get filled? It would have to listen to
the UNIBUS the memory is on. So I'm guessing that's that those connectors and
boards are for.
Note that there has to be a signal from FastBus (anyone know the correct
capitalization for that?) which tells the CPU if the MS11 has a given address
or not (given the way the MS11 can be configured as to size and address), so
the cache board could use that line to tell the CPU whether or not the
location in question is in the cache.
Noel
22 Jul
22 Jul
11:35 p.m.
-----Original Message-----
From: cctalk [mailto:cctalk-bounces at classiccmp.org] On Behalf Of Noel
Chiappa via cctalk
Sent: Sunday, July 22, 2018 2:07 PM
To: cctalk at classiccmp.org
Cc: jnc at mercury.lcs.mit.edu
Subject: Re: Strange third party board in PDP-11/45
- MS11-B Engineering Drawings
About all we're missing are the MS11-A/C data board engineering drawings.
(The control board is in the MS11-B prints.)
-----
Note that the schematics clearly show that the memory controller has direct
access to both the Fastbus and Unibus B, and thus slot 21 (and 16) is wired
for the purpose.
So why have OTT cables to both slots 26 /27 AB?
Perhaps the narrow cable goes to slot 27 to pick up some additional Unibus B
signals, and the wider cable to slot 26 to pick up a larger set of Unibus A
signals equivalent to those to which it already has direct access for Unibus
B)..
Is this the way that those OTT cables are wired Mattis?
From the ABLE marketing literature:
CACHE/ 45 (CACHE BUFFER MEMORY) INSTALLS IN: PDP-11/45, -11/50 and -11/55
CAPACITY: 2048 byte (1 K word).
ENHANCEMENT FACTOR: Run time reductions to 50% (100% speed improvement) are
achievable.
CACHE PARITY: Automatically goes off-line in event of any data error.
RANGE SELECTION: User may optimize hit ratio by upper/lower limit switch
settings.
SPECIAL FEATURE: Cache/ 45 can be enabled via software or console switches.
Presumably that's what Mattis has in-hand.
-----
23 Jul
23 Jul
9:57 p.m.
-----Original Message-----
From: Paul Birkel [mailto:pbirkel at gmail.com]
Sent: Monday, July 23, 2018 2:36 AM
To: General Discussion: On-Topic and Off-Topic Posts
Subject: RE: Strange third party board in PDP-11/45
...
From the ABLE marketing literature:
CACHE/ 45 (CACHE BUFFER MEMORY) INSTALLS IN: PDP-11/45, -11/50 and -11/55
CAPACITY: 2048 byte (1 K word).
ENHANCEMENT FACTOR: Run time reductions to 50% (100% speed improvement) are
achievable.
CACHE PARITY: Automatically goes off-line in event of any data error.
RANGE SELECTION: User may optimize hit ratio by upper/lower limit switch
settings.
SPECIAL FEATURE: Cache/ 45 can be enabled via software or console switches.
Presumably that's what Mattis has in-hand.
-----
https://books.google.com/books?id=hYD3sny2NzEC&pg=PA23&lpg=PA23&…
uter+technology+ACT+DEC+%22CACHE/45%22&source=bl&ots=b15iACJbMd&sig=oLMrJMn2
qEFmxiKSMIhpLF5qYnk&hl=en&sa=X&ved=2ahUKEwjcyvzi87TcAhVOw1kKHdc5A8kQ6AEwAHoE
CAIQAQ#v=onepage&q=ABLE%20Computer%20technology%20ACT%20DEC%20%22CACHE%2F45%
22&f=false
Computerworld, Page 23, July 26, 1976
ACT Has PDP-11/45 Buffer
SANTA ANA, Calif. - Able Computer Technology (ACT) has a 2K-byte cache
buffer for use with the Digital Equipment Corp. POP-11/45.
The Cache/45 is contained on a single printed circuit board that plugs into
the
system's chassis.
Buffer control is provided over every core memory address location on the
Unibus. A switch within the memory buffer permits a choice of either on-line
or off-line operation, the company said.
The buffer costs $7 ,000. ACT is at I 538-E Chestnut St., Santa Ana, Calif.
92705.
(Somewhat strange use of the expressions "on-line" and "off-line"
operation,
IMO.)
I presume that the reason for "single printed circuit board" is that only a
single "normal" slot is occupied.
paul
10:23 p.m.
At one time DEC left it up to the branches whether or not to maintain
non-DEC parts. The switch would help by disabling the device while running
diags and doing other maintenance. Nobody wanted to be liable if a non-DEC
board had to be pulled.
Paul
On Mon, Jul 23, 2018 at 11:57 PM, Paul Birkel via cctalk <
cctalk at classiccmp.org> wrote:
-----Original Message-----
From: Paul Birkel [mailto:pbirkel at gmail.com]
Sent: Monday, July 23, 2018 2:36 AM
To: General Discussion: On-Topic and Off-Topic Posts
Subject: RE: Strange third party board in PDP-11/45
...
From the ABLE marketing literature:
CACHE/ 45 (CACHE BUFFER MEMORY) INSTALLS IN: PDP-11/45, -11/50 and -11/55
CAPACITY: 2048 byte (1 K word).
ENHANCEMENT FACTOR: Run time reductions to 50% (100% speed improvement) are
achievable.
CACHE PARITY: Automatically goes off-line in event of any data error.
RANGE SELECTION: User may optimize hit ratio by upper/lower limit switch
settings.
SPECIAL FEATURE: Cache/ 45 can be enabled via software or console switches.
Presumably that's what Mattis has in-hand.
-----
https://books.google.com/books?id=hYD3sny2NzEC&pg=PA23&
lpg=PA23&dq=ABLE+Comp
uter+technology+ACT+DEC+%22CACHE/45%22&source=bl&ots=
b15iACJbMd&sig=oLMrJMn2
qEFmxiKSMIhpLF5qYnk&hl=en&sa=X&ved=2ahUKEwjcyvzi87TcAhVOw1kKHdc5A
8kQ6AEwAHoE
CAIQAQ#v=onepage&q=ABLE%20Computer%20technology%20ACT%
20DEC%20%22CACHE%2F45%
22&f=false
Computerworld, Page 23, July 26, 1976
ACT Has PDP-11/45 Buffer
SANTA ANA, Calif. - Able Computer Technology (ACT) has a 2K-byte cache
buffer for use with the Digital Equipment Corp. POP-11/45.
The Cache/45 is contained on a single printed circuit board that plugs into
the
system's chassis.
Buffer control is provided over every core memory address location on the
Unibus. A switch within the memory buffer permits a choice of either
on-line
or off-line operation, the company said.
The buffer costs $7 ,000. ACT is at I 538-E Chestnut St., Santa Ana, Calif.
92705.
(Somewhat strange use of the expressions "on-line" and "off-line"
operation,
IMO.)
I presume that the reason for "single printed circuit board" is that only a
single "normal" slot is occupied.
paul
2304
days inactive
2306
days old
3 comments
3 participants
participants (3)
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jnc＠mercury.lcs.mit.edu -
pbirkel＠gmail.com -
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