On 10/01/2014 12:52 PM, Tony Duell wrote:
The problem comes when you have a 16H8 or 16L8 which
contains sequential
logic (the feedback terms allow this). AFAIK there is no 'preload'
funciton for these devices, so you can't force all the inputs to the
logic array.
Exactly--the idea is that these clocked devices can (and usually do)
have a memory. On a simple unclocked combinatorial PLD, you can safely
say that for any input or combination of inputs, there is a given
output. Repeat the input values as many times as you want, it always
comes out the same way.
With a PLD with a latch in it, a given output state can not only depend
on the input state, but also any state "memorized" by the device--and
there can be many of those, each dependent on any previous state and the
current set of inputs. All of the sudden, "exhaustive" begins taking
on an exponential character.
One problem that I ran into early on was determining which lines were
inputs and which were outputs, as well as which were tri-state and under
what conditions. Certain lines are always inputs and certain lines are
always outputs, so that gives a starting point.
By feeding lines through resistors and "pushing" those (with logic 1's
and 0's) and observing the behavior of the pins to see which lines were
always high-impedance for all input values and which lines were
high-impedance only for certain sets of inputs, it's possible to make a
determination. This does complicate the process somewhat, but not
tremendously. Obviously, it helps if you know what's connected to the
PAL, but that's not always the case.
--Chuck