No, the addresses are sent on the address lines (A0-A9 in the case of a normal I/O address on a PC, although IIRC, the 80x86 acutally uses A0-A15, it's just that _most_ ISA cards ignore the top few address lines for I/O cycles). I've not got the data sheet on this disk controller chip to hand, but typically, you'll find that the low few address lines go to inputs on the chip to select different internal registers. The higher lines are decoded to provide a chip select signal. An example may help. Suppose the particular I/O chip has 8 internal registers, it will therefore have 3 address inputs to select one of the 8. And suppose you want it to appear at I/O addresses 370-377 hex. A0, A1, A2 are wired to the address inputs on the chip A3 to A9 are wired to an address decoder circuit which asserts chip select when the signals are in the following states A9 A8 A7 A6 A5 A4 A3 1 1 0 1 1 1 0 _One_ way to do that would be to invery A7 and A3 (say by using 74LS04 NOT gates) and then to NAND the outputs of those inverters with the other 5 signals (a 74LS30 8-input NAND is useful here!). Note that this produces a low at the output of the NAND gate for the desired address range, and that most chip select signals are active low. It's also generally necessary to include the Address Enable signal and the I/O Read and I/O Write signals at some point. Very often this address decoding is done by a PAL or a PROM, or even worse inside an ASIC. You may be able to program a new device to move thigns to new addresses. In some cases, inverting some of the address inputs to the PAL/PROM will help, but this will generally 'move' all devices selected by that PAL/PROM. Maybe you'll have to design a new address decoder circuit and kludge it on somehow. Before trying that, you'll want to look at the schematics for a few simple ISA cards to see how the address decoding is generally done. -tony

On Saturday 18 February 2006 18:04, Kelly Leavitt wrote: The easiest way to do this, is to trace the address lines from the ISA port to the address decoder chip, and to swap some of the address line inputs to the chip around. Eg, if you swapped A7 and A6, with J8/1 closed, you'd get 3B0, swapping A7 and A5 would get you 3D0 as an address, A7 and A4 would get 3E0, A7 and A8 get you 2F0, A7 and A9 get you 1F0, etc. According to the document I'm looking at, 3B0-3B7 is also used by the MDA, 3D0 is used by the CGA/EGA/VGA, 1F0 is the primary IDE controller address, and 3E0 and 2F0 seems to be generally unused. Pat -- Purdue University ITAP/RCAC --- http://www.rcac.purdue.edu/ The Computer Refuge --- http://computer-refuge.org