8-bitters and multi-whatever - test-drb@ccmp.vtda.org

14 Sep 2007

...

Subject: Re: 8-bitters and multi-whatever
   From: "Roy J. Tellason" <rtellason at verizon.net>
   Date: Thu, 13 Sep 2007 17:33:33 -0400
     To: "General Discussion: On-Topic and Off-Topic Posts" <cctalk at
classiccmp.org>

On Wednesday 12 September 2007 07:43, Allison wrote:
  Mine started when I needed to get stuff from the
various CP/M systems
 that even when they had disks were incompatable hard sector to soft
 or 8 and 5.25. I started with serial peer to peer as in pipmodem and
 similar. 
Pipmodem?  That's a new one on me,  though the name is pretty suggestive. 
PIP has an area that the user can modify as an aux device outside 
those in the bios (or part of the bios).  Try doing a google on it.

...

  Later I did a two system resource sharing that
grew to allow up to a
 potential 256 systems. In '82 the whole thing peaked with a multiprocessor
 S100 crate with intercommunications via pooled memory.  
How was that handled in the hardware,  particularly with regard to contention 
for access?  I vaguely recall running across some multiport memory chips,  
but their capacity wasn't anywhere near what was currently in use that didn't 
have that feature. 
Real simple the pooled memory was often just a block of ram in common space 
and each cpu had it's comminications area and a doorbell register to signal 
that it needs to check it's pool. The protocal was A writes to Bs com area,
A hits Bs doorbell, A waits for doorbell and goes back to check As comm area.
Since S100 bus arbitration allowed only one bus master and none of the areas
overlapped it was very robust. It relied on bus mastering, a clear protocal 
and the "doobell register" to do attention requested signaling and keeps the
message block from read part way while being written. By assigning buffers
that do not overlap it made sure one cpu didn't corrupt anthers message.   
However for systems without bus master arbitation other schemes existed too.
S100 IEE696 had bus master arbitration and Compupro and others used that 
scheme.  It was by no means the only way.

For example Ampro (AmproLB+) used the SCSI/sasi bus for it's communications 
between CPUs.

Allison