Dram is "refreshed" or rewritten to keep the little capacitors from discharging. They are organized as rows and columns. The refresh process only needs a pass through every row within so many milliseconds (varies with part)to do the trick. Now as rams get bigger you natually have more rows and columns. But, while they were getting bigger they were also getting more complex. Sounds bad, huh? Well no! The complexity is in the logic to do the refresh. Parts in the late 4164 (64k) design life and later started turning up with their own internal refresh counter and by wiggling the RAS/ or CAS/ the right way and often enough they refresh themselves. Most of the big (41256 and larger) parts have this as well as most of the 30pin SIMM (256k, 1m and 4m, 16m) parts. Now for a lot more detail and great explantion see Tim Olmstead's DRAM paper available from Gaby's site http://www.cpm.z80.de/ "The Unofficial CP/M Web Site". Worthwhile reading for anyone mystified by Drams or phobic about them. FYI: the paper is Z80 centric but those that know it also know it only does 128 refresh. Yet, big (megabyte) rams can be hung off it due to the newer parts doing their own refresh thing. It all translates to other CPUs as well including those that don't do refresh for you at all (non z80 family). Allison