8 Dec
2016
8 Dec
'16
4:30 p.m.
From: Rich Alderson
9-track tapes on the PDP-10 used one of the following
encodings:
What about 7-track, any idea? I would assume 6 x 6-bit tape frames per 36-bit
word, but that's just a guess.
Noel
8 Dec
8 Dec
8:08 p.m.
Not meaning to throw things to far off but on my
NC4000 machine( 16 bit ), I found ByteSwap useful enough that I had it
hard wired.
I have an old computer that was intended to do FFTs. It has a
complete bit order swap, MSB to LSB, instruction.
All interesting.
Dwight
________________________________
From: cctalk <cctalk-bounces at classiccmp.org> on behalf of Noel Chiappa <jnc at
mercury.lcs.mit.edu>
Sent: Thursday, December 8, 2016 1:30:48 PM
To: cctalk at classiccmp.org
Cc: jnc at mercury.lcs.mit.edu
Subject: Re: Odd "endianness" [was Re: RE: Base 64 posts to the list]
From: Rich Alderson
9-track tapes on the PDP-10 used one of the following
encodings:
What about 7-track, any idea? I would assume 6 x 6-bit tape frames per 36-bit
word, but that's just a guess.
Noel
9:53 p.m.
On 12/08/2016 05:08 PM, dwight wrote:
Not meaning to throw things to far off but on my
NC4000 machine( 16 bit ), I found ByteSwap useful enough that I had it
hard wired.
I have an old computer that was intended to do FFTs. It has a
complete bit order swap, MSB to LSB, instruction.
Well, there's the PowerPC "endian" mode (settable in the MSR)--but it's
just "sort of"--the little-endian mode simply XORs the lower 3 bits of
the address with 111 (i.e. "flips them").
--Chuck
11:46 p.m.
I have an old
computer that was intended to do FFTs. It has a
complete bit order swap, MSB to LSB, instruction.
Well, there's the PowerPC "endian" mode (settable in the MSR)--but
it's
just "sort of"--the little-endian mode simply XORs the lower 3 bits of
the address with 111 (i.e. "flips them").
9 Dec
9 Dec
1:25 a.m.
On 12/08/2016 08:46 PM, Cameron Kaiser wrote:
Or you could use the PowerPC byte-swapped instructions (lwbrx, etc.)
Forgot to mention the ARM CPUs/MCUs. Supports both, for people who
can't make up their mind.
--Chuck
I have an old computer that was intended to do FFTs.
It has a
complete bit order swap, MSB to LSB, instruction.
Well, there's the PowerPC "endian" mode (settable in the MSR)--but
it's just "sort of"--the little-endian mode simply XORs the lower 3
bits of the address with 111 (i.e. "flips them"). 
10:02 a.m.
On Dec 9, 2016, at 1:25 AM, Chuck Guzis <cclist at
sydex.com> wrote:
On 12/08/2016 08:46 PM, Cameron Kaiser wrote:
Or you could use the PowerPC byte-swapped instructions (lwbrx, etc.)
Forgot to mention the ARM CPUs/MCUs. Supports both, for people who
can't make up their mind.
Rather than "can't make up their mind", a good reason to have selectable
endian processors is that the best choice may depend on the application. So for embedded
systems in particular, it's good to be able to pick which you want.
paul
I have an old computer that was intended to do FFTs.
It has a
complete bit order swap, MSB to LSB, instruction.
Well, there's the PowerPC "endian" mode (settable in the MSR)--but
it's just "sort of"--the little-endian mode simply XORs the lower 3
bits of the address with 111 (i.e. "flips them").
1:50 p.m.
On 12/09/2016 07:02 AM, Paul Koning wrote:
Rather than "can't make up their mind",
a good reason to have
selectable endian processors is that the best choice may depend on
the application. So for embedded systems in particular, it's good to
be able to pick which you want.
My quip was an attempt at levity.
One interesting aspect of the later ARM (e.g. Cortex M3) are the
"reverse" instructions:
REV reverses the byte order in a 32-bit words. Thus, ABCD becomes DCBA.
REV16 reverses the byte order in each halfword of a 32 bit word, ABCD
becomes BADC.
REVSH reverses the byte order in the low-order halfword and sign extends
to 32 bits. Thus ABCD becomes SSDC (with S symbolizing the extended
sign bit)
RBIT reverses the bit order in a 32 bit word.
So lots of choices for those who feel that variety is the spice of life.
--Chuck
3:15 p.m.
On 12/08/2016 07:08 PM, dwight wrote:
Not meaning to throw things to far off but on my
NC4000 machine( 16 bit ), I found ByteSwap useful enough that I had it
hard wired.
I have an old computer that was intended to do FFTs. It has a
complete bit order swap, MSB to LSB, instruction.
Yup, this is to implement the "butterfly" mirroring of the addresses for
the FFT.
Jon
14 Dec
14 Dec
6:54 a.m.
Noel Chiappa wrote:
A reasonable guess, and one I'd make too. But I don't know either.
Supposedly, many ITS backups were made to 7-track tapes. That became a
problem when the old tape drives started to fail, and available new tape
drives were only 9-track.
9-track tapes
on the PDP-10 used one of the following encodings:
What about 7-track, any idea? I would assume 6 x 6-bit tape frames per
36-bit word, but that's just a guess. 
2:11 p.m.
From: Lars Brinkhoff
Sent: Wednesday, December 14, 2016 3:54 AM
Noel Chiappa wrote:
>> 9-track tapes on the PDP-10 used one of the
following encodings:
> What about 7-track, any idea? I would assume 6 x
6-bit tape frames per
> 36-bit word, but that's just a guess.
A reasonable guess, and one I'd make too. But I
don't know either.
According to the monitor calls manuals for both Tops-10 and TOPS-20, as
well as the manual specifically on tape labels etc., that's a very good
guess, and a correct one.
Supposedly, many ITS backups were made to 7-track
tapes. That became a
problem when the old tape drives started to fail, and available new tape
drives were only 9-track.
The same issue occurred at SAIL for the early WAITS backups prior to the
introduction of a KL-10 into the system (which grew from a PDP-6 to a
PDP-10/PDP-6 to a KL-10/KA-10/166, then shrank to a KL-10/KA-10 down to
a KL-10 only). The KL-10 had TU-78 drives on an RH20.
AIUI, the older backup tapes were refrangled onto new 9-track media before
the KA-10 and its drives were retired.
Rich
Rich Alderson
Vintage Computing Sr. Systems Engineer
Living Computer Museum
2245 1st Avenue S
Seattle, WA 98134
mailto:RichA at LivingComputerMuseum.org
http://www.LivingComputerMuseum.org/
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