You've got to be pulling my chain... (Ethernet) - test-drb@ccmp.vtda.org

10 Apr 1998

<       Allison, this was private email, but I figure this may be

OOPs, though I did check the header as classiccmp...?

<       like the 11/23 and 11/73 line should run this BSD variant as
<       well... what I want to know is, did the kernel fit into 64K in
<       one segment, or did they spread the kernel across segment
<       bounderies?  If so, how? 

The kernel never fit in 64kb as the pdp11 is word addressed also the MMU
operates on 4kb pages. Also the top 4kbytes are IO space.  So the idea of 
the kernel fitting in 64k is not relevent.  The real question was did it 
fit in the 11/44 or 45 who only had 256k (18bit addresses) space.  The 
11/23 and later Qbus machines were Q22 (4mb address space).  The larger 
space means more available ram that can be used without resorting to 
swapping (or at least less frequently).

Also PDP11s come in two other flavors, those with I&D space and those 
without.  The 11/23 and 11/34 are those without.  The 44, 45, 70, 73, 
83 and others have I&D which means that Instructions and Data spaces can 
be seperate doubling the amount of memory available.  Added to that is 
user and system space (memory protection between processes).  So it's 
possible for a PDP11 to actaully address four distinct areas of memory 
that are non-overlapping and all 64k in size.  Practical considerations 
limit it to less than that but it's nearly so and likely they would 
overlap as well.

<       I mean, I could see overlays (in the kernel... blech!), but I
<       don't remember the 11 supporting long long jumps... and address
<       value was 16 bits, period.  Still, I was never great at 11

True of all segmented address machines.  The larger 256k or 4mb space is 
broken into  pages of which up to 8 are mapped into the 16bit address
space.  To do a long jump what is really done is the cpu remapped the
needed page into logical space and does a 16bit jump to that page.
The top 4 bits determine what page register is addressed and the contents
of that register is appended to the lower 12 bit to form the larger 
address needed to manage a 4mb space.  

It takes 8 MMU registers and uses the content of the reg plus the 16bit 
address to form an address in physical space.

<       assembly.  Could someone here give a good detailed account of
<       PDP-11 segment mapping support?  Could my stack and register
<       values be retained and follow while moving from segment to
<       segment?  And how the hell did you tell the memory manager you
<       wanted to pop to another segment, anyway?

yes!  A detailed discussion would wear out my fingers typing it.

Sufficient that it was able to address more than 64k and while different 
than the 8088 or 286 in both cases the 16 bit address space was extended 
by argumenting the basic addressing and not extending the basic register 
set.

I'm currently building a system using the z80 cousin called the z280 that
can address 16mb of ram and the basic addressing is still 64k argumented 
by a MMU.

Allison