When the bus master requests block mode DMA, it inserts BS7 when inserting the first DIN. If the slave is capable of block mod DMA, it inserts REF when inserting RPLY. The master removes BS7 when inserting the last DIN to finish the block mode DMA. My question is, what will happen if the master finishes the DMA cycle early? The same question is, what will happen if the master keeps BS7 inserted when inserting the last DIN? Will the slave malfunction? It seems a small violation of the protocol. It seems the bus master needs to predict the availability of Data otherwise. Thanks. __________________________________ Do you Yahoo!? SBC Yahoo! - Internet access at a great low price. http://promo.yahoo.com/sbc/