chips - test-drb@ccmp.vtda.org

29 Jun 1999

There have, in recent years come to be other manufacturers offering the
PALCE version of the popular LATTICE GAL's.  Cypress is, indeed, among them.

As for the feedback, if you use pins 1 or 11 as something other than CLOCK
or /OE, as they were used in the 16-series PALs, then the input path from
them preempted the feedback from these end macrocells.  I wouldn't remember
that, except that PALASM slapped my wrist for it a couple of times early in
my experience with them, so, like the dog who once pee'd on the electric
fence, I remember that.  There are other little "gotchas" with the various
versions of these parts.

Dick

-----Original Message-----
From: Pete Turnbull &lt;pete(a)dunnington.u-net.com&gt;
To: Discussion re-collecting of classic computers
&lt;classiccmp(a)u.washington.edu&gt;
Date: Tuesday, June 29, 1999 12:52 AM
Subject: Re: chips

...
 On Jun 28, 17:41, Richard Erlacher wrote:
  Subject: Re: chips
 SInce these are electrically eraseable it's of no consequence what the
 previous program was.  These parts can be viewed as a relplacement for the
  entire 16xN series where x=L or R and N ranges
from 4 to 8.  They can
 effectively emulate/replace 16L8, 16R4, 16R6 and 16R8 with a few exceptions.
  The macrocells associated with pins 19 and 12
have no feedback path of their
  own, i.e. it must be via the adjacent macrocell. 
The data book (these are
  AMD/Vantis parts) for the Lattice GAL parts will
explain it adequately if
 you can't lay hands on an AMD databook. 
They're not necessarily AMD; they could be Cypress parts, or one of a few
other manufacturers.  Unfortunately, not all use the same erase or
programming algorithms (Lattice, National Semiconductor, and SGS Thomson
 use one algorithm; AMD, Texas, Cypress, Altera and ICT use others).

Why do you say that pins 12 and 19 have no feedback path of their own?
 They do in my data sheets...

--

Pete Peter Turnbull
 Dept. of Computer Science
 University of York 