16 Apr
2007
16 Apr
'07
3:16 p.m.
hacking time...
Is parity generation a simple case of chaining exclusive-or gates for the
required number of data bits? e.g. for 8 data lines:
d0 --+
XOR--+
d1 --+ |
XOR--+
d2 --+ | |
XOR--+ |
d3 --+ |
XOR--- parity
d4 --+ |
XOR--+ |
d5 --+ | |
XOR--+
d6 --+ |
XOR--+
d7 --+
(possibly inverted at the end, depending on requirement for odd/even parity)
... I think that works, but thought I'd ask for list wisdom first :) I don't
have a parity generator IC (LS280?) handy, but if the above works then a
couple of LS86 chips would do the job*.
*possibly a little slower than a "proper" LS280, but that's not critical for
what I had in mind.
cheers
Jules
16 Apr
16 Apr
3:47 p.m.
Jules Richardson wrote:
hacking time...
Is parity generation a simple case of chaining exclusive-or gates for
the required number of data bits? e.g. for 8 data lines:
d0 --+
XOR--+
d1 --+ |
XOR--+
d2 --+ | |
XOR--+ |
d3 --+ |
XOR--- parity
d4 --+ |
XOR--+ |
d5 --+ | |
XOR--+
d6 --+ |
XOR--+
d7 --+
(possibly inverted at the end, depending on requirement for odd/even
parity)
... I think that works, but thought I'd ask for list wisdom first :) I
don't have a parity generator IC (LS280?) handy, but if the above works
then a couple of LS86 chips would do the job*.
*possibly a little slower than a "proper" LS280, but that's not critical
for what I had in mind.
cheers
Jules
Jules, your understanding is absolutely correct.
11:08 p.m.
hacking time...
Is parity generation a simple case of chaining exclusive-or gates for the
required number of data bits? e.g. for 8 data lines:
d0 --+
XOR--+
d1 --+ |
XOR--+
d2 --+ | |
XOR--+ |
d3 --+ |
XOR--- parity
d4 --+ |
XOR--+ |
d5 --+ | |
XOR--+
d6 --+ |
XOR--+
d7 --+
(possibly inverted at the end, depending on requirement for odd/even parity)
Yes, exactly that...
Your method :
(((d0 XOR d1) XOR (d2 XOR d3)) XOR ((d4 XOR d5) XOR (d6 XOR d7)))
is logially equvalent to
(d0 XOR (d1 XOR (d2 XOR (d2 XOR (d3 XOR (d4 XOR (d5 XOR (d6 XOR d7]
but the latter has a longer maximum propagation delay.
Incidentally, my TTL data books (heck, the newest over 20 years old now)
show gate level scheamtics for the more complex chips (and component
level scehamtics for the simple gates). Looking up '74LS280' in there
shows the intenral structure. I don't know if that data sheet is
availabke on-line, say on digchip or sowmehre.
-tony
11:58 p.m.
On 4/16/07, Tony Duell <ard at p850ug1.demon.co.uk> wrote:
Incidentally, my TTL data books (heck, the newest over 20 years old now)
show gate level scheamtics for the more complex chips (and component
level scehamtics for the simple gates). Looking up '74LS280' in there
shows the intenral structure. I don't know if that data sheet is
availabke on-line, say on digchip or sowmehre.
Here's one source: http://focus.ti.com/lit/ds/symlink/sn74ls280.pdf
11:34 p.m.
Thats taught me something today :)
But what if you have 7 data bits? How would it work then?
Regards,
Andrew B
aliensrcooluk at yahoo.co.uk
PS. Thanks to all who answered my chemistry question on another thread.
Jules Richardson <julesrichardsonuk at yahoo.co.uk> wrote:
hacking time...
Is parity generation a simple case of chaining exclusive-or gates for the
required number of data bits? e.g. for 8 data lines:
d0 --+
XOR--+
d1 --+ |
XOR--+
d2 --+ | |
XOR--+ |
d3 --+ |
XOR--- parity
d4 --+ |
XOR--+ |
d5 --+ | |
XOR--+
d6 --+ |
XOR--+
d7 --+
(possibly inverted at the end, depending on requirement for odd/even parity)
... I think that works, but thought I'd ask for list wisdom first :) I don't
have a parity generator IC (LS280?) handy, but if the above works then a
couple of LS86 chips would do the job*.
*possibly a little slower than a "proper" LS280, but that's not critical for
what I had in mind.
cheers
Jules
11:50 p.m.
Thats taught me something today :)
But what if you have 7 data bits? How would it work then?
Try something like :
d0 --+
XOR--+
d1 --+ |
XOR--+
d2 --+ | |
XOR--+ |
d3 --+ |
XOR--- parity
d4 --+ |
XOR--+ |
d5 --+ | |
XOR--+
) |
d6--------+
and invert the output as necessary to get the required odd/even parity.
Cue the well-knwon thread on multi-way light swtiches (which are
logically parity trees).
-tony
17 Apr
17 Apr
12:16 a.m.
On 16 Apr 2007 at 23:34, Andrew Burton wrote:
But what if you have 7 data bits? How would it work
then?
Decide if you want even or odd parity, then tie the unused input
either high or low.
I think that the early databooks also show how to make a parity
generator from a bipolar ROM.
Cheers,
Chuck
7:53 p.m.
I think that the early databooks also show how to make
a parity
generator from a bipolar ROM.
You can make any combinatorial logic circuit from a ROM. Using one for a
parity tree seems ridiculously over-complex, though.
You cna also do it with multiplexers. I think you can make an N+1 input
parity circuit using an 2^N input mux and one NOT gate, and an N+2 input
one using the 2^N input mux, 1 NOT gate and 1 XOR gate.
-tony
11:22 p.m.
On 17 Apr 2007 at 19:53, Tony Duell wrote:
Motorola marketed the MC4041 as something very much like this; it was
a pre-programmed version of an XC170 ROM. Of course, they were also
suggesting that the same ROM be used as a BCD-to-7 segment decoder
(MC4039) and a 3-bit-to-8 demux (MC4038). Note that I said "early"
:)
Cheers,
Chuck
I think that
the early databooks also show how to make a parity
generator from a bipolar ROM.
You can make any combinatorial logic circuit from a ROM. Using one for a
parity tree seems ridiculously over-complex, though.
18 Apr
18 Apr
10:49 p.m.
On 17 Apr 2007 at 19:53, Tony Duell wrote:
Motorola marketed the MC4041 as something very much like this; it was
a pre-programmed version of an XC170 ROM. Of course, they were also
suggesting that the same ROM be used as a BCD-to-7 segment decoder
(MC4039) and a 3-bit-to-8 demux (MC4038). Note that I said "early"
:)
That last oen is totally ridiculous IMHO, given that a ROM contains an
n->2^n decoder to select an a particular location in the ROM determined
by the states of the n address lioes.
And if, as you said, it was early, there's even less of a justification.
Trasnistors were more expensive back then...
-tony
I think
that the early databooks also show how to make a parity
generator from a bipolar ROM.
You can make any combinatorial logic circuit from a ROM. Using one for a
parity tree seems ridiculously over-complex, though.
6490
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6492
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