Dave McGuire <mcguire(a)neurotica.com> wrote: No, at 4 or 8 clock cycles per instruction, unfortunately. Microchip claims that their chips are "pipelined", but they don't understand the meaning of the word. They divide down the clock into four internal phases, for instruction fetch, operand read, ALU, and result writeback. This is documented in some of their data sheets. In a truly pipelined CPU, they would do the operand read for instruction n+1 at the same time as the ALU operation for instruction n and the result writeback for instruction n-1. Actually, although they don't describe it that way, I think that they do a limited sort of pipelining, in that I think they actually use all four clocks for each instruction fetch, and just latch the result on phase 1. That way their ROM doesn't have to be as fast. The Scenix SX18 and SX28 parts, which are enhanced clones of the PIC16C5x family, have a "turbo" mode that is fully pipelined, so most instructions really do run in one clock cycle (rather than four). Also, they run at up to 100 MHz. They would be much more suitable for implementing a floppy disk controller.

Dwight Elvey <elvey(a)hal.com> wrote: Certainly you could. The main difference is that the Scenix parts are available for $5, come in DIP packages that are easy to prototype with, and that there are a lot of cheap development tools.