30 Jun
2014
30 Jun
'14
8:34 p.m.
Trying to help out some folks on the cbm hackers list read the 6500/1
ROM in the 1520 plotter. It turns out, based on the data sheet, there
is a way to put the CPU in a "test" mode and send opcode data to the
CPU, and we are going to try to to use that to read the contents of the ROM.
The test mode is engaged by placing 10V on the RESET pin.
And, you know, before tonight, I thought I was at least average on
transistor theory and application, but I'm stumped, and I'm hoping
someone can help.
To support 3 voltages on RESET (0,5,10), I placed a 2n3904 with the
collector on the RESET pin, and emitter on ground. base is biased via
10K resistor to an IO pin on an AVR uC I am using the drive the CPU.
That works fine.
TO support putting 10V on the RESET, I built a PNP/NPN pair. PNP has E
on 10V, C on RESET, and B is biased via 10K to C on NPN. B on NPN is
biased via 100K to another IO pin, and E is at GND.
The thought was that driving the IO pin high, the NPN will pull the PNP
base to ground, thus turning on the PNP, and placing 10V on RESET.
And, it works, but it "fades". Over 2ms, RESET slow falls from 10V to
~6V. If I turn the transistor off and then back on, the cycle repeats.
So, I obviously am doing it wrong, but I can't seem to determine where
my theory fails me, and I thought someone on here could help (or suggest
another simple way to support 3 voltages on the RESET pin under SW control.
Jim
--
Jim Brain
brain at jbrain.com
www.jbrain.com
30 Jun
30 Jun
10:59 p.m.
On 1 July 2014 05:34, Jim Brain <brain at jbrain.com> wrote:
[...]
The test mode is engaged by placing 10V on the RESET pin.
[...]
So, I obviously am doing it wrong, but I can't
seem to determine where my
theory fails me, and I thought someone on here could help (or suggest
another simple way to support 3 voltages on the RESET pin under SW control.
Jim
Why not use Optoisolators? I assume per-unit cost is not an issue here :-)
Joachim
--
Joachim Thiemann :: http://jthiem.bitbucket.org ::
http://signalsprocessed.blogspot.com
11:32 p.m.
On 2014 Jun 30, at 8:34 PM, Jim Brain wrote:
Trying to help out some folks on the cbm hackers list
read the
6500/1 ROM in the 1520 plotter. It turns out, based on the data
sheet, there is a way to put the CPU in a "test" mode and send
opcode data to the CPU, and we are going to try to to use that to
read the contents of the ROM.
The test mode is engaged by placing 10V on the RESET pin.
And, you know, before tonight, I thought I was at least average on
transistor theory and application, but I'm stumped, and I'm hoping
someone can help.
To support 3 voltages on RESET (0,5,10), I placed a 2n3904 with the
collector on the RESET pin, and emitter on ground. base is biased
via 10K resistor to an IO pin on an AVR uC I am using the drive the
CPU. That works fine.
TO support putting 10V on the RESET, I built a PNP/NPN pair. PNP
has E on 10V, C on RESET, and B is biased via 10K to C on NPN. B
on NPN is biased via 100K to another IO pin, and E is at GND.
The thought was that driving the IO pin high, the NPN will pull the
PNP base to ground, thus turning on the PNP, and placing 10V on RESET.
And, it works, but it "fades". Over 2ms, RESET slow falls from 10V
to ~6V. If I turn the transistor off and then back on, the cycle
repeats.
So, I obviously am doing it wrong, but I can't seem to determine
where my theory fails me, and I thought someone on here could help
(or suggest another simple way to support 3 voltages on the RESET
pin under SW control.
The datasheets (at least those found at http://www.commodore.ca/
commodore-manuals/mos-commodore-semiconductor-group-6500-6502-
processor-cpu-manual/) are rather poorly specced, they don't go into
just what the special characteristics or input structure of that
reset pin are - how the +10V is sensed internally.
Normally, you don't want to drive chip inputs at > Vcc because input
protection diodes or parasitic on-chip diode junctions kick into
forward conduction, drawing current from the chip Vcc, out the input,
through (your PNP transistor), to +10. That clamps the voltage on the
input at Vcc + (~ 0.6 or something greater), in the vicinity of the
+6V you mention.
This reset input is supposedly (the datasheet is contradictory) able
to tolerate excess voltage, but it may need current limiting.
If the PNP-E = +10V and PNP-C = ~ +6V, then the PNP transistor is
saturating. With the bias resistors you have the PNP CE current could
be (off-the-top-o-the-head calc) maybe 100mA (!) through the reset
input(!). Do you have any indication in your setup of what is
happening with current on the +10 supply and +5 supply?
You might try putting a current limiting resistor of say 10K in the
PNP-C to reset-pin line.
The reset input may still clamp at ~ +6V, but it will be safer for
the chip.
You could/should also add a (say) 1K R from PNP-C to +5 to give a
decent pull-up when both your reset drive transistors are off. (In
proper operation), that should speed up transitions to 'high'/+5 on
the reset input.
1 Jul
1 Jul
6:22 p.m.
New subject: Reading code from 6500/1 CPU (was: Noob analog question (no doubt simple))
On 7/1/2014 1:32 AM, Brent Hilpert wrote:
On 2014 Jun 30, at 8:34 PM, Jim Brain wrote:
The datasheets (at least those found at
http://www.commodore.ca/commodore-manuals/mos-commodore-semiconductor-group…)
are rather poorly specced, they don't go into just what the special
characteristics or input structure of that reset pin are - how the
+10V is sensed internally.
I know, but that's all we have...
Normally, you don't want to drive chip inputs at > Vcc because input
protection diodes or parasitic on-chip diode junctions kick into
forward conduction, drawing current from the chip Vcc, out the input,
through (your PNP transistor), to +10. That clamps the voltage on the
input at Vcc + (~ 0.6 or something greater), in the vicinity of the
+6V you mention.
This reset input is supposedly (the datasheet is contradictory) able
to tolerate excess voltage, but it may need current limiting.
Well, I didn't
have the CPU in the circuit at that point (I wanted it
right before I subjected the CPU). It turns out that I had the bias
wrong on the PNPs and NPN. I upped the current from the IO pin to the
NPN B via a 1K, and tied the E to ground through a 5K. I can now see
perfectly stable 10V and 5V voltages at the RESET pin.
You could/should also add a (say) 1K R from PNP-C to +5 to give a
decent pull-up when both your reset drive transistors are off. (In
proper operation), that should speed up transitions to 'high'/+5 on
the reset input.
I used 10K, which did as you suggest.
Sadly, my test code is not doing anything, so we must not have enough
understanding of the internals. The internal clock is 1/2 external, and
I am running the CPU at 250kHz to ensure enough time for the uC to do
things.
But, thanks for the suggestions. I thought for sure I was losing it...
Jim
--
Jim Brain
brain at jbrain.com
www.jbrain.com
5 Jul
5 Jul
7:23 p.m.
New subject: Reading MOS 6500/1 ROM (was: Re: Noob analog question (no doubt simple))
Just an update to note that I was successful in reading the ROM out of
the MOS 6500/1 using the test mode. I used an ATMEGA32 to drive the
opcodes into PORTC, driving the RESET line to 10V, and reading data from
the PORTA on the unit. The opcodes loaded data from the ROM and put it
on the PORTA as output.
I dumped both the CBM 1520 Plotter ROM versions (-01 and -03).
Jim
--
Jim Brain
brain at jbrain.com
www.jbrain.com
8:02 p.m.
New subject: Reading MOS 6500/1 ROM (was: Re: Noob analog question (no doubt simple))
On Sat, Jul 5, 2014 at 10:23 PM, Jim Brain <brain at jbrain.com> wrote:
Just an update to note that I was successful in
reading the ROM out of the
MOS 6500/1 using the test mode. I used an ATMEGA32 to drive the opcodes
into PORTC, driving the RESET line to 10V, and reading data from the PORTA
on the unit. The opcodes loaded data from the ROM and put it on the PORTA
as output.
Perfect.
I dumped both the CBM 1520 Plotter ROM versions (-01
and -03).
Excellent!
-ethan
6 Jul
6 Jul
1:16 p.m.
New subject: Reading MOS 6500/1 ROM (was: Re: Noob analog question (no doubt
Just an update to note that I was successful in reading the ROM out of
the MOS 6500/1 using the test mode. I used an ATMEGA32 to drive the
Well done!
I dumped both the CBM 1520 Plotter ROM versions (-01
and -03).
The 1520 is the little 4-pen Alps mechanism, isn't it?
Are these ROM images avaialbe for download anywhere?
-tony
8:29 p.m.
New subject: Reading MOS 6500/1 ROM
On 7/6/2014 3:16 PM, Tony Duell wrote:
http://singularcrew.hu/temp/1520-01.asm.html
http://singularcrew.hu/temp/1520-03.asm.html
Or a simplified version that should work on all assemblers:
http://singularcrew.hu/temp/1520-01-plain.asm
http://singularcrew.hu/temp/1520-03-plain.asm
But these are temp locations and the disassembly is still being refined, so I would
caution against grabbing these now and not checking back later.
Binary:
https://dl.dropboxusercontent.com/u/58002657/cbm/1520/p8-pf.bin
Infofile (pretty basic):
https://dl.dropboxusercontent.com/u/58002657/cbm/1520/p8-pf.infofile
Raw disassembly (infofile still crude):
https://dl.dropboxusercontent.com/u/58002657/cbm/1520/p8-pf.s
The above is only the -01 binary. I can send the -03 files, but you'd
need to stitch them together (I could only dump them in 256 byte chunks).
At some point soon, there will be a web page someone is creating to put
all of this stuff in a common location, including the binaries and a
schematic to dump them yourself.
Jim
--
Jim Brain
brain at jbrain.com
www.jbrain.com
Just an update
to note that I was successful in reading the ROM out of
the MOS 6500/1 using the test mode. I used an ATMEGA32 to drive the
Well done!
I dumped both the CBM 1520 Plotter ROM versions
(-01 and -03).
The 1520 is the little 4-pen Alps mechanism, isn't it?
Are these ROM images avaialbe for download anywhere?
-tony
7 Jul
7 Jul
12:55 p.m.
New subject: Reading MOS 6500/1 ROM
Or a simplified version that should work on all
assemblers:
http://singularcrew.hu/temp/1520-01-plain.asm
http://singularcrew.hu/temp/1520-03-plain.asm
Thanks... I've downlded those, just to have a local copy,. but I'll
almost certainly not doi anything with them for quite some time. I guess
the updated/cleaned-up version will be avaialble before then...
-tony
3820
days inactive
3826
days old
8 comments
5 participants
participants (5)
-
ard＠p850ug1.demon.co.uk -
brain＠jbrain.com -
ethan.dicks＠gmail.com -
hilpert＠cs.ubc.ca -
joachim.thiemann＠gmail.com