17 Dec
2018
17 Dec
'18
1:52 p.m.
From: Paul Koning
For that matter, core memory details such as
destructive read weren't
visible to the CPU
Umm, not quite. If you'd said 'core memory details such as destructive read
weren't visible to the _program_', you'd have been 100% correct.
But as I suspect you know, just overlooked, most (all?) of the -11 CPU's do
use 'read-modify-write' cycles on the bus (DATIP in UNIBUS terms, DATIO in
QBUS) where possible precisely for the benefit of core memory with its
destructive readout. (And there's some hair for interlocking the multiple
CPU's on the -11/74 which I don't recall off the top of my head.)
And I have a vague memory of something similar on other early DEC machines;
probably some -8 models.
Noel
17 Dec
17 Dec
1:58 p.m.
On Dec 17, 2018, at 1:52 PM, Noel Chiappa via cctalk
<cctalk at classiccmp.org> wrote:
No, that doesn't invalidate what I said. DATAIP/DATAO on the Unibus doesn't
depend on the destructive read property. It works just fine with DEC semiconductor
memory. It is perfectly valid to implement DATAIP as if it were DATAI, so that
transaction simply becomes a read followed by a write.
The reason it existed is that it allows core memory to optimize the timing, by running a
"half cycle", omitting the restore part. But the DATAO supplies the new content
of the word, and so long as the memory does that write you're all set.
If PDP-11s ever did a DATAIP without a DATAO, you'd be able to tell the difference
between core and semiconductor memory by reading the location afterwards and looking for
non-zero. But conforming Unibus masters don't do that.
paul
From: Paul Koning
For that matter, core memory details such as
destructive read weren't
visible to the CPU
Umm, not quite. If you'd said 'core memory details such as destructive read
weren't visible to the _program_', you'd have been 100% correct.
But as I suspect you know, just overlooked, most (all?) of the -11 CPU's do
use 'read-modify-write' cycles on the bus (DATIP in UNIBUS terms, DATIO in
QBUS) where possible precisely for the benefit of core memory with its
destructive readout. (And there's some hair for interlocking the multiple
CPU's on the -11/74 which I don't recall off the top of my head.) 
2 p.m.
On Dec 17, 2018, at 10:52 AM, Noel Chiappa via cctalk
<cctalk at classiccmp.org> wrote:
But it does *no* harm if the underlying memory does *not* have a destructive
read-out. Otherwise all of those (even DEC branded) MOS memory boards
wouldn?t work. ;-)
The DATIP and friends were an optimization implemented in the bus protocol
to allow for it to take advantage of the behavior of core. However, nothing
breaks if the memory doesn?t implement a destructive read-out.
TTFN - Guy
From: Paul Koning
For that matter, core memory details such as
destructive read weren't
visible to the CPU
Umm, not quite. If you'd said 'core memory details such as destructive read
weren't visible to the _program_', you'd have been 100% correct.
But as I suspect you know, just overlooked, most (all?) of the -11 CPU's do
use 'read-modify-write' cycles on the bus (DATIP in UNIBUS terms, DATIO in
QBUS) where possible precisely for the benefit of core memory with its
destructive readout. (And there's some hair for interlocking the multiple
CPU's on the -11/74 which I don't recall off the top of my head.)
And I have a vague memory of something similar on other early DEC machines;
probably some -8 models.
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