Hi, I've been playing about with the HDL code for the floppy reader (after a "short break") and started thinking about how the VCO Sync/Inhibit line on the data separator should be driven. At the moment it's driven permanently high; this seems to work OK insofar as the sync detector (which is why the datasep is there -- to extract a clock signal for the MFM data stream) will pick up SYNC-A1 signals and the data seems to be valid. What I don't know is if this is how things are supposed to be done... The uPD765 and 827x datasheets are predictably rather sketchy on this front... All they really say is that the VCO line inhibits the VCO in the PLL, which would have the effect of allowing the PLL's loop filter to discharge, and reset it to a predetermined state. What they don't say is under what conditions the FDC will do that... So I guess the million dollar question is what I should do with said VCO line. Wire it to /INDEX via an inverter to reset the PLL on every rotation? Or just wire it to VCC (VCO enabled) and leave it? Thanks, -- Phil. classiccmp at philpem.me.uk http://www.philpem.me.uk/