15 Dec
2018
15 Dec
'18
1:01 p.m.
FRAM or MRAM. I make extensive use of them in my projects.
Everspin has a few (all SMT and 3.3v). As I recall they run ~$20/ea for 4Mb (512K x 8 or
256K x 16).
TTFN - Guy
On Dec 15, 2018, at 1:22 AM, Rod G8DGR via cctalk
<cctalk at classiccmp.org> wrote:
I have an idea to produce an MM-8 clone using RAM that acts like core when turned off.
Can anybody suggest a chip that will do this?
Rod Smallwood
Sent from Mail for Windows 10
15 Dec
15 Dec
1:55 p.m.
On 12/15/18 10:01 AM, Guy Sotomayor Jr via cctalk wrote:
FRAM or MRAM. I make extensive use of them in my
projects.
Everspin has a few (all SMT and 3.3v). As I recall they run ~$20/ea for 4Mb (512K x 8 or
256K x 16).
As neither MRAM nor FRAM requires a write-after-read refresh, I fail to
see the "realism" in this that couldn't be satisfied with simple
battery-backed RAM or even flash-backed RAM.
Yes, MRAM is magnetic, but ti's not the same principle as real core.
FWIW,
Chuck
1:58 p.m.
Chuck,
FRAM is destructive read on the die, from what I understand. It's just that
the onboard controller takes care of it for you, much like a core subsystem.
Thanks,
Jonathan
On Sat, Dec 15, 2018 at 1:55 PM Chuck Guzis via cctalk <
cctalk at classiccmp.org> wrote:
On 12/15/18 10:01 AM, Guy Sotomayor Jr via cctalk
wrote:
FRAM or MRAM. I make extensive use of them in my
projects.
Everspin has a few (all SMT and 3.3v). As I recall they run ~$20/ea for
4Mb (512K
x 8 or 256K x 16).
As neither MRAM nor FRAM requires a write-after-read refresh, I fail to
see the "realism" in this that couldn't be satisfied with simple
battery-backed RAM or even flash-backed RAM.
Yes, MRAM is magnetic, but ti's not the same principle as real core.
FWIW,
Chuck
3:15 p.m.
If you want the real deal you can always make a driver out of a bunch of
H-bridge ICs and an old core plane. I'll skip suggesting you weave your own
core...
On Sat, Dec 15, 2018, 2:01 PM systems_glitch via cctalk <
cctalk at classiccmp.org wrote:
Chuck,
FRAM is destructive read on the die, from what I understand. It's just that
the onboard controller takes care of it for you, much like a core
subsystem.
Thanks,
Jonathan
On Sat, Dec 15, 2018 at 1:55 PM Chuck Guzis via cctalk <
cctalk at classiccmp.org> wrote:
On 12/15/18 10:01 AM, Guy Sotomayor Jr via cctalk
wrote:
> FRAM or MRAM. I make extensive use of them in my projects.
>
> Everspin has a few (all SMT and 3.3v). As I recall they run ~$20/ea
for
4Mb (512K x 8 or 256K x 16).
As neither MRAM nor FRAM requires a write-after-read refresh, I fail to
see the "realism" in this that couldn't be satisfied with simple
battery-backed RAM or even flash-backed RAM.
Yes, MRAM is magnetic, but ti's not the same principle as real core.
FWIW,
Chuck
8:42 p.m.
On Sat, Dec 15, 2018 at 11:55 AM Chuck Guzis via cctalk <
cctalk at classiccmp.org> wrote:
On 12/15/18 10:01 AM, Guy Sotomayor Jr via cctalk
wrote:
FRAM requires write-after-read refresh, but it's done internally to the
part. That's why FRAM has limited read endurance; each read also does a
write. FRAM endurance is typically 10^14 cycles (check the datasheet of a
specific part), which is adequate for most uses.
FRAM or MRAM. I make extensive use of them in my
projects.
Everspin has a few (all SMT and 3.3v). As I recall they run ~$20/ea for
4Mb (512K
x 8 or 256K x 16).
As neither MRAM nor FRAM requires a write-after-read refresh, I fail to
see the "realism" in this that couldn't be satisfied with simple
battery-backed RAM or even flash-backed RAM.
16 Dec
16 Dec
2:21 p.m.
On Dec 15, 2018, at 1:55 PM, Chuck Guzis via cctalk
<cctalk at classiccmp.org> wrote:
On 12/15/18 10:01 AM, Guy Sotomayor Jr via cctalk wrote:
The key question is what the level of accuracy of the emulation is.
If you simply want non-volatile memory, the obvious answer is SRAM with battery backup and
a small FPGA to do the interfacing.
If you need to emulate the destructive read, the same but with a slightly more complex
FPGA.
It's hard to see -- other than "because you can" -- why it's useful to
emulate the destructive read. Read/modify/write will work without the destructive read,
so long as a write simply overwrites what was in the word. The only place I can think of
where the destructive read propery is useful is in CDC 6000 series peripheral processor
memory, at least when you're debugging PP programs that get stuck -- a memory dump
taken after a restart will show a zero at the point of the hang.
paul
FRAM or MRAM. I make extensive use of them in my
projects.
Everspin has a few (all SMT and 3.3v). As I recall they run ~$20/ea for 4Mb (512K x 8 or
256K x 16).
As neither MRAM nor FRAM requires a write-after-read refresh, I fail to
see the "realism" in this that couldn't be satisfied with simple
battery-backed RAM or even flash-backed RAM.
Yes, MRAM is magnetic, but ti's not the same principle as real core.
17 Dec
17 Dec
1:40 a.m.
On 12/16/18 11:21 AM, Paul Koning wrote:
If you simply want non-volatile memory, the obvious
answer is SRAM with battery backup and a small FPGA to do the interfacing.
I proposed nvRAM - CMOS SRAM backed by cell-for-cell flash. Loads SRAM
from flash on power-up and stores into flash at
power-down. All that's
needed is a capacitor to extend the power-down cycle a
bit.
Very fast, available in 8 to 32-bit wide architectures, up to 16Mbit per
package.
Claims to be guaranteed for 1M power cycles and doesn't require a battery.
--Chuck
9:50 a.m.
On Sunday (12/16/2018 at 10:40PM -0800), Chuck Guzis via cctalk wrote:
On 12/16/18 11:21 AM, Paul Koning wrote:
These are pretty neat. Took me a bit to find an example. They like to
call it "NvSRAM",
http://www.cypress.com/search/psg/1259#/?_facetShow=ss_ppart_family,ss_pint…
which is a typical 32K x 8, 5V device.
The "flash" subsystem is something they call SONOS / QuantumTrap technology.
Takes 8mS to STORE the SRAM to the backing store at power down and 20mS
to RECALL it at power up.
The storage cap is typically 68uF so nothing monster.
Chris
--
Chris Elmquist
If you simply want non-volatile memory, the
obvious answer is SRAM with battery backup and a small FPGA to do the interfacing.
I proposed nvRAM - CMOS SRAM backed by cell-for-cell flash. Loads SRAM
from flash on power-up and stores into flash at power-down. All that's
needed is a capacitor to extend the power-down cycle a bit.
Very fast, available in 8 to 32-bit wide architectures, up to 16Mbit per
package.
Claims to be guaranteed for 1M power cycles and doesn't require a battery.
12:51 p.m.
On Dec 16, 2018, at 10:40 PM, Chuck Guzis via cctalk
<cctalk at classiccmp.org> wrote:
On 12/16/18 11:21 AM, Paul Koning wrote:
Except it is *much* more expensive than MRAM. 32x8 NVSRAM is $18.50 in qty 1 from
Digikey.
A 64Kx16 MRAM is $11.84 in qty 1 from Digikey. MRAM requires no additional circuitry so
that
also reduces the overall cost (and has unlimited write endurance).
If it sounds like I?m harping on MRAM, maybe I am. I?ve looked at the various
technologies in
detail (what?s available, cost, interfacing, etc, etc) for years and for anything that
requires
non-volatility, MRAM wins until you get into seriously large sizes at which point you need
to
go to FLASH for economics.
TTFN - Guy
If you simply want non-volatile memory, the
obvious answer is SRAM with battery backup and a small FPGA to do the interfacing.
I proposed nvRAM - CMOS SRAM backed by cell-for-cell flash. Loads SRAM
from flash on power-up and stores into flash at power-down. All that's
needed is a capacitor to extend the power-down cycle a bit.
Very fast, available in 8 to 32-bit wide architectures, up to 16Mbit per
package.
Claims to be guaranteed for 1M power cycles and doesn't require a battery.
1:09 p.m.
On Dec 17, 2018, at 12:51 PM, Guy Sotomayor Jr via
cctalk <cctalk at classiccmp.org> wrote:
I'll go along with that. I worked on a storage product that needed non-volatile
memory in modest sizes for tracking transaction states. The first product used FRAM for
that, the second used SRAM backed by a small battery ("coin cell") and the third
used MRAM. All worked fine. FRAM supposedly has endurance limits but they are high
enough they weren't a concern. The main issue was the size limits, at least at the
time (2003-ish).
For simplicity, battery backed SRAM should be just as good as SRAM. In any case, you
presumably will need a CPLD or small FPGA for the interface protocol conversion.
paul
On Dec 16, 2018, at 10:40 PM, Chuck Guzis via
cctalk <cctalk at classiccmp.org> wrote:
On 12/16/18 11:21 AM, Paul Koning wrote:
Except it is *much* more expensive than MRAM. 32x8 NVSRAM is $18.50 in qty 1 from
Digikey.
A 64Kx16 MRAM is $11.84 in qty 1 from Digikey. MRAM requires no additional circuitry so
that
also reduces the overall cost (and has unlimited write endurance).
If it sounds like I?m harping on MRAM, maybe I am. I?ve looked at the various
technologies in
detail (what?s available, cost, interfacing, etc, etc) for years and for anything that
requires
non-volatility, MRAM wins until you get into seriously large sizes at which point you
need to
go to FLASH for economics. If you simply want non-volatile memory, the
obvious answer is SRAM with battery backup and a small FPGA to do the interfacing.
I proposed nvRAM - CMOS SRAM backed by cell-for-cell flash. Loads SRAM
from flash on power-up and stores into flash at power-down. All that's
needed is a capacitor to extend the power-down cycle a bit.
Very fast, available in 8 to 32-bit wide architectures, up to 16Mbit per
package.
Claims to be guaranteed for 1M power cycles and doesn't require a battery. 
1:13 p.m.
I've seen a lot of talk about memory technologies, but as far as I can see,
no one has offered any complete solutions.
One already exists, thanks to the efforts of Steve Lafferty, Vince
Slyngstad, and others.
http://so-much-stuff.com/pdp8/32KOmnibus/32KOmnibus.php
Yes, it uses a battery. FPGAs and CPLDs are not needed (though a CPLD could
reduce all of the logic and drivers to a single chip, with the ATF1508).
Numerous Omnibus PDP-8 owners have these cards, and I swear by them in my
machines. I'd much rather keep a hefty load off of the power supply and
free up 11 card slots, especially in my 8/M.
Maybe with enough interest, Vince would consider doing another run of
boards.
Thanks,
Kyle
3:29 p.m.
On 12/17/18 9:51 AM, Guy Sotomayor Jr wrote:
Except it is *much* more expensive than MRAM. 32x8
NVSRAM is $18.50 in qty 1 from Digikey.
A 64Kx16 MRAM is $11.84 in qty 1 from Digikey. MRAM requires no additional circuitry so
that
also reduces the overall cost (and has unlimited write endurance).
nvSRAM is sole-sourced technology, so there's a premium.
The crazy thing is that I was using the Xicor NOVRAM in the late
70s-early 80s. I still have a parts drawer full of X2444 8-pin DIPs
from about that time. The technology appears to be
roughly the same.
Xicor got gobbled up by Intersil V2; Intersil V1 got gobbled up by
Harris and then spun off again as Intersil V2 and then gobbled up by
Renesas.
You really need a program to tell the players apart.
FWIW, there seems to be increasing interest in NVDIMMs:
https://www.electronicdesign.com/industrial-automation/why-are-nvdimms-sudd…
I have no doubt that by the time they're wiping the drool from my face
and wheeling me in front of the TeeVee to pass the time, that engineers
will be discussing their favorite 20 psec. 8 exabyte non-volatile RAM
chips...
--Chuck
15 Dec
15 Dec
10:09 p.m.
On 12/15/2018 01:01 PM, Guy Sotomayor Jr via cctech wrote:
FRAM or MRAM. I make extensive use of them in my
projects.
Everspin has a few (all SMT and 3.3v). As I recall they run ~$20/ea for 4Mb (512K x 8 or
256K x 16).
TTFN - Guy
> On Dec 15, 2018, at 1:22 AM, Rod G8DGR via cctalk <cctalk at classiccmp.org>
wrote:
>
> I have an idea to produce an MM-8 clone using RAM that acts like core when turned
off.
> Can anybody suggest a chip that will do this?
>
> Rod Smallwood
>
>
My call on this is that cmos static ram 4Bit wide does the job well I
have 32K of it in my PDP-8 to
get past possible failure of hard to find and get core.? A Panasonic
BR-1 lithium cell has enough
capacity at the measured drain for about 6-7 years and the Dallas power
management chip
makes it a non hack.? Flash, EEprom and Magnetic FRAM and MRAM) types
have many unacceptable
properties for a random access read write memory.? It makes no
difference to the PDP8(ILEFMA)
that read is not destructive as it will write back as needed anyway.
There is a design on the 'net for using CMOS ram in a straight forward
buildable array for Omnibus
with battery back up that is fine.? Don;t get wraped around the axle
about RMW as any sufficiently
fast ram can do that without wearout.? And compared to core it doesn't
take much speed.
EEprom and Flash work fine for read mostly disks or disk simulators.
Allison
11:23 p.m.
On Dec 15, 2018, at 7:09 PM, allison via cctech
<cctech at classiccmp.org> wrote:
On 12/15/2018 01:01 PM, Guy Sotomayor Jr via cctech wrote:
I think you?re mistaken about FRAM and MRAM. They are byte oriented devices
and are designed to replace SRAM + battery. Which in my mind makes them
preferable as they reduce parts count. The current MRAM has unlimited write
endurance (same as SRAM) and depending upon the part is 35-55ns access/cycle
time. FRAM has a similar access time but requires an internal restore so it?s cycle
time is about 2x (one of the reasons I prefer MRAM now).
TTFN - Guy
FRAM or MRAM. I make extensive use of them in my
projects.
Everspin has a few (all SMT and 3.3v). As I recall they run ~$20/ea for 4Mb (512K x 8 or
256K x 16).
TTFN - Guy
> On Dec 15, 2018, at 1:22 AM, Rod G8DGR via cctalk <cctalk at classiccmp.org>
wrote:
>
> I have an idea to produce an MM-8 clone using RAM that acts like core when turned
off.
> Can anybody suggest a chip that will do this?
>
> Rod Smallwood
>
>
Flash, EEprom and Magnetic FRAM and MRAM) types
have many unacceptable
properties for a random access read write memory. 
16 Dec
16 Dec
12:19 a.m.
Sent from Mail for Windows 10
From: allison via cctech
Sent: 16 December 2018 03:08
To: cctech at classiccmp.org
Subject: Re: Core memory emulator using non volatile ram.
On 12/15/2018 01:01 PM, Guy Sotomayor Jr via cctech wrote:
FRAM or MRAM. I make extensive use of them in my
projects.
Everspin has a few (all SMT and 3.3v). As I recall they run ~$20/ea for 4Mb (512K x 8 or
256K x 16).
TTFN - Guy
> On Dec 15, 2018, at 1:22 AM, Rod G8DGR via cctalk <cctalk at classiccmp.org>
wrote:
>
> I have an idea to produce an MM-8 clone using RAM that acts like core when turned
off.
> Can anybody suggest a chip that will do this?
>
> Rod Smallwood
>
>
My call on this is that cmos static ram 4Bit wide does the job well I
have 32K of it in my PDP-8 to
get past possible failure of hard to find and get core.? A Panasonic
BR-1 lithium cell has enough
capacity at the measured drain for about 6-7 years and the Dallas power
management chip
makes it a non hack.? Flash, EEprom and Magnetic FRAM and MRAM) types
have many unacceptable
properties for a random access read write memory.? It makes no
difference to the PDP8(ILEFMA)
that read is not destructive as it will write back as needed anyway.
There is a design on the 'net for using CMOS ram in a straight forward
buildable array for Omnibus
with battery back up that is fine.? Don;t get wraped around the axle
about RMW as any sufficiently
fast ram can do that without wearout.? And compared to core it doesn't
take much speed.
EEprom and Flash work fine for read mostly disks or disk simulators.
Allison
Sheesh!! Well what a response.
This stems from my (so far) successful major over haul of my PDP-8/e.
I found one failed 7474 and one failed 8881 ? replaced and now working.
I think I have the rim loader toggled in and will attempt to send a paper tape image from
Hyperterm
Strangely I do have at least three genuine complete 4k memory sets.
However I began to think would it be possible to create a close copy of an 8/e out of
modern parts.
As you all know I make front panels so that?s not a problem.
I did manage to copy my (distorted) bezel in resin.
A friend has been able to 3D print toggle switch leavers that fit and work.
Vince Sylngstat has done a console board PCB layout.
Power supply clearly not a problem.
So what?s left? Case?
Well I have one of those and I suspect a sheet metal shop would not have a problem
Finally the big one ? Omnibus and the connectors its made from. A 3D printing candidate?
I?m going to autopsy a busted connector and see how they are constructed inside.
Objectives
The basic board set as original. M8300, M8310, M8320 etc.
Same form factor
Plug compatible ? but board contents can differ from original
The idea is replace one item at time until you no longer have any DEC parts.
Yup a FAKE-8
I may even need a label ?No part in this PDP-8/e computer was manufactured by digital
equipment corporation?
Rod Smallwood
11:36 a.m.
Anyone building? 8 omnibus? batter? backed up core? replacement? currently? that? is?
available off the? shelf reasonably for? ?8 m,e and? f? (( Smaller? size? board? than the?
?8a? ?would accept? ?for memory as I? remember..))
?
Have? a 8 m or? f? in my? den on a? shelf...? ?as? as I? best? remember? it? 20? years
ago? had? 4 k or? ?flaky? core in it.? might? be? fun? to play? with.?
?
Alas? there? might? me other things? wrong on other boards? by now? too....
?
Ed#
?
?
?
In a message dated 12/16/2018 6:44:55 AM US Mountain Standard Time, cctalk at
classiccmp.org writes:
?
On 12/15/2018 01:01 PM, Guy Sotomayor Jr via cctech wrote:
FRAM or MRAM. I make extensive use of them in my
projects.
Everspin has a few (all SMT and 3.3v). As I recall they run ~$20/ea for 4Mb (512K x 8 or
256K x 16).
TTFN - Guy
> On Dec 15, 2018, at 1:22 AM, Rod G8DGR via cctalk <cctalk at classiccmp.org>
wrote:
>
> I have an idea to produce an MM-8 clone using RAM that acts like core when turned
off.
> Can anybody suggest a chip that will do this?
>
> Rod Smallwood
>
>
My call on this is that cmos static ram 4Bit wide does the job well I
have 32K of it in my PDP-8 to
get past possible failure of hard to find and get core.? A Panasonic
BR-1 lithium cell has enough
capacity at the measured drain for about 6-7 years and the Dallas power
management chip
makes it a non hack.? Flash, EEprom and Magnetic FRAM and MRAM) types
have many unacceptable
properties for a random access read write memory.? It makes no
difference to the PDP8(ILEFMA)
that read is not destructive as it will write back as needed anyway.
There is a design on the 'net for using CMOS ram in a straight forward
buildable array for Omnibus
with battery back up that is fine.? Don;t get wraped around the axle
about RMW as any sufficiently
fast ram can do that without wearout.? And compared to core it doesn't
take much speed.
EEprom and Flash work fine for read mostly disks or disk simulators.
Allison
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